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ds07-13712-4e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90470 series mb90473/474/477/478/f474l/f474h n descriptions the fujitsu mb90470 series is a 16-bit general-purpose microcontroller designed for consumer products and other process control applications requiring high-speed and real-time processing. the f 2 mc-16lx cpu core instruction set retains the at architecture of the f 2 mc* 1 family, with additional instruc- tions for use with high-level languages, expanded addressing mode, enhanced multiply and divide instructions, and full bit processing. also included is a built-in 32-bit accumulator for long-word processing. peripheral resources built into the mb90470 series include 8/16-bit ppg, expanded i/o serial interface, uart, 10-bit a/d converter, 16-bit input-output timer, 8/16-bit up-counter, pwc timer, i 2 c* 2 interface, dtp/external interrupt, chip select, and 16-bit reload timer. *1 : f 2 mc is an abbreviation for fujitsu flexible microcontroller, and is a registered trademark of fujitsu, ltd. *2 : i 2 c license : this product includes licensing of philips i 2 c patents if used by the customer in an i 2 c system subject to the i 2 c standard specifications established by philips. n packages 100-pin plastic qfp 100-pin plastic lqfp (fpt-100p-m06) (fpt-100p-m05)
mb90470 series 2 n features ? clocks minimum instruction execution time : 50.0 ns at 5 mhz base oscillation with 4 multiplier (internal operation at 20 mhz/3.3 v 0.3 v) 62.5 ns at 4 mhz base oscillation with 4 multiplier (internal operation at 16 mhz/3.0 v 0.3 v) uses pll clock multiplier. ? maximum memory size 16 mbytes ? instruction set optimized for control applications handles bit, byte, word, long-word data 23 standard addressing modes 32-bit accumulator for enhanced high-precision calculation signed multiply-divide and expanded reti instructions ? instruction system compatible with high - level language ( c ) multitasking system stack pointer instruction set correlation and barrel shift instructions ? non-multi bus or multi-bus compatible ? program patch function (for two address pointers) ? improved execution speed 4-byte queue ? powerful interrupt functions 8 external interrupt functions with 8-level programmable priority ? data transfer functions ( m m m m dma or extended intelligent i/o service ) 16 channels maximum m dma maximum assured operation frequency : 16 mhz extended intelligent i/o service maximum assured operation frequency : 20 mhz ? built - in rom flash versions : 256 kb, mask rom versions : 128 kb/256 kb ? built - in ram 10 kb/16 kb ? general purpose ports 84 ports maximum (includes 16 ports with input pull-up resistance setting, 14 ports with output open drain setting) ? a / d converter rc sequential comparator type, 8 channels 10-bit resolution, conversion time 4.65 m s (at 20 mhz operation) ? i 2 c interface 1 channel ? m m m m pg 1 channel ? uart 1 channel ? i / o expansion serial interface ( sio ) 2 channels ? 8 / 16 - bit up / down timer 1 channel ? 16 - bit pwc 3 channels (including 2-channel input comparison function) (continued)
mb90470 series 3 (continued) ? 16 - bit reload timer 1 channel (8-bit 2-channel, 16-bit 1-channel mode switching function provided) ? 16 - bit input - output timer 2-channel input capture, 6-channel output compare, 1-channel free run timer ? 2 built-in clock generator systems ? low power modes stop, sleep, cpu intermittent mode, watch mode, etc. ? package options qfp100/lqfp100 ? process cmos technology ? supply voltage can operate on 3 v single supply systems (with 5 v interface provided by some pins with 3/5 v dual-supply capability)
mb90470 series 4 n product lineup (continued) parameter part number mb90f474l mb90f474h mb90473 mb90474 rom capacity flash 256 kb flash 256 kb maskrom 128 kb maskrom 256 kb ram capacity 16 kb 16 kb 10 kb 16 kb cpu functions basic instructions instruction bit length instruction length data bit length minimum instruction execution time : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 62.5 ns (with 16 mhz machine clock) ports general purpose input/output ports : 84 max general purpose input/output ports (cmos output) general purpose input/output ports (built-in pull-up resistance) general purpose input/output ports (n-ch open drain) uart stop-start synchronized : 1 channel 8/16-bit ppg timer 8-bit 6-channel/16-bit 3-channel 8/16-bit up-down counter/timer two 8-bit up-down counters with 6 event input pins two 8-bit reload/compare registers 16-bit input/ out- put timers 16 - bit free - run timer channel : 1 overflow interrupt output compare ( ocu ) channels : 6 pin input source : from compare register match signal input capture (icu) channels : 2 register rewritten from pin input (rising/falling/both edges) dtp/external interrupt circuit external interrupt pins : 8 channels (set to edge or level correlation) i/o expansion serial interface 2-channel, built-in i 2 c interface 1-channel, built-in time base timer 18-bit counter interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 mhz) a/d converter conversion accuracy : 8/10-bit switchable single conversion mode (converts selected channel 1 time only) scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) continuous conversion mode (converts selected channels continuously) stop conversion mode (converts selected channel, stops and repeats) watchdog timer reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 mhz) low power (standby) modes sleep, stop, cpu intermittent, watch mode process cmos notes flash model, low voltage version (f = 10 mhz or less at v cc = 2.4 v) flash model, high voltage version (f = 20 mhz) mask version mask version emulator dedicated power supply ????
mb90470 series 5 (continued) parameter part number mb90477 mb90478 mb90v470b rom capacity maskrom 256 kb maskrom 256 kb ? ram capacity 8 kb 8 kb 16 kb cpu functions basic instructions instruction bit length instruction length data bit length minimum instruction execution time : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bit, 16-bit : 50 ns (with 20 mhz machine clock) ports general purpose input/output ports : 84 max general purpose input/output ports (cmos output) general purpose input/output ports (built-in pull-up resistance) general purpose input/output ports (n-ch open drain) uart stop-start synchronized : 1 channel 8/16-bit ppg timer 8-bit 6-channel/16-bit 3-channel 8/16-bit up-down counter/timer two 8-bit up-down counters with 6 event input pins two 8-bit reload/compare registers 16-bit input/ output timers 16-bit free-run timer channel : 1 overflow interrupt output compare (ocu) channels : 6 pin input source : from compare register match signal input capture (icu) channels : 2 register rewritten from pin input (rising/falling/both edges) dtp/external interrupt circuit external interrupt pins : 8 channels (set to edge or level correlation) i/o expansion serial interface 2-channel, built-in i 2 c interface 1-channel, built-in time base timer 18-bit counter interrupt cycle : 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (minimum times, at base oscillator frequency 4 mhz) a/d converter conversion accuracy : 8/10-bit switchable single conversion mode (converts selected channel 1 time only) scan conversion mode (converts multiple consecutive channels, programmable up to 8 channels) continuous conversion mode (converts selected channels continuously) stop conversion mode (converts selected channel, stops and repeats) watchdog timer reset interval : 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum times, at base oscillator frequency 4 mhz) low power (standby) modes sleep, stop, cpu intermittent, watch mode process cmos notes mask version mask version without i 2 c built-in interface eva function user pin emulator dedicated power supply ?? included
mb90470 series 6 n pin assignments (top view) (fpt-100p-m06) 1 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20/ppg0 p25/a21/ppg1 p26/a22/ppg2 p27/a23/ppg3 p30/a00/ain0 p31/a01/bin0 v ss p32/a02/zin0 p33/a03/ain1 p34/a04/bin1 p35/a05/zin1 p36/a06/pwc0 p37/a07/pwc1 p40/a08/sin2 p41/a09/sot2 p42/a10/sck2 p43/a11/mt00 p44/a12/mt01 v cc 5 p45/a13/extc p46/a14/out4 p47/a15/out5 p70/sin0 p71/sot0 p72/sck0 p73/tin0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x0a x1a p57/clk rst p56/rdy p55/hak p54/hrq p53/wrh p52/wrl p51/rd p50/ale pa3/out3 pa2/out2 pa1/out1 pa0/out0 p97/in1 p96/in0 p95/ppg5 p94/ppg4 p93/frck/adtg/cs3 p92/sck1/cs2 p91/sot1/cs1 p90/sin1/cs0 p87/irq7 p86/irq6 p85/irq5 p84/irq4 p83/irq3 p82/irq2 md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 p74/tot0 p75/pwc2 p76/scl p77/sda av cc avrh av ss p60/an0 p61/an1 p62/an2 p63/an3 vss p64/an4 p65/an5 p66/an6 p67/an7 p80/irq0 p81/irq1 md0 md1 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p17/ad15/d15 p16/ad14/d14 p15/ad13/d13 p14/ad12/d12 p13/ad11/d11 p12/ad10/d10 p11/ad09/d09 p10/ad08/d08 p07/ad07/d07 p06/ad06/d06 p05/ad05/d05 p04/ad04/d04 p03/ad03/d03 p02/ad02/d02 p01/ad01/d01 p00/ad00/d00 v cc 3 x1 x0 v ss 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
mb90470 series 7 (top view) (fpt-100p-m05) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 rst p56/rdy p55/hak p54/hrq p53/wrh p52/wrl p51/rd p50/ale pa3/out3 pa2/out2 pa1/out1 pa0/out0 p97/in1 p96/in0 p95/ppg5 p94/ppg4 p93/frck/adtg/cs3 p92/sck1/cs2 p91/sot1/cs1 p90/sin1/cs0 p87/irq7 p86/irq6 p85/irq5 p84/irq4 p83/irq3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p22/a18 p23/a19 p24/a20/ppg0 p25/a21/ppg1 p26/a22/ppg2 p27/a23/ppg3 p30/a00/ain0 p31/a01/bin0 v ss p32/a02/zin0 p33/a03/ain1 p34/a04/bin1 p35/a05/zin1 p36/a06/pwc0 p37/a07/pwc1 p40/a08/sin2 p41/a09/sot2 p42/a10/sck2 p43/a11/mt00 p44/a12/mt01 v cc 5 p45/a13/extc p46/a14/out4 p47/a15/out5 p70/sin0 p71/sot0 p72/sck0 p73/tin0 p74/tot0 p75/pwc2 p76/scl p77/sda av cc avrh av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p80/irq0 p81/irq1 md0 md1 md2 p82/irq2 p21/a17 p20/a16 p17/ad15/d15 p16/ad14/d13 p15/ad13/d13 p14/ad12/d12 p13/ad11/d11 p12/ad10/d10 p11/ad09/d09 p10/ad08/d08 p07/ad07/d07 p06/ad06/d06 p05/ad05/d05 p04/ad04/d04 p03/ad03/d03 p02/ad02/d02 p01/ad01/d01 p00/ad00/d00 v cc 3 x1 x0 v ss x0a x1a p57/clk 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
mb90470 series 8 n pin description (continued) lqfp : fpt-100p-m05 package qfp : fpt-100p-m06 package pin no. pin name circuit type description lqfp qfp 80 82 x0 a oscillator pin 81 83 x1 a oscillator pin 78 80 x0a a 32 khz oscillator pin 77 79 x1a a 32 khz oscillator pin 75 77 rst b reset input pin 83 to 90 85 to 92 p00 to p07 c (cmos) general purpose input/output ports. set the pull-up resistance setting register (rdr0) to add pull-up resistance (rd00-rd07 = 1 ) . (not valid when set for output) ad00 to ad07 in multiplex mode, these pins function as external address/ data bus lower input/output pins. d00 to d07 in non-multiplex mode, these pins function as external data bus lower output pins. 91 to 98 93 to 100 p10 to p17 c (cmos) general purpose input/output ports. set the pull-up resistance setting register (rdr1) to add pull-up resistance (rd10-rd17 = 1 ) . (not valid when set for output) ad08 to ad15 in multiplex mode, these pins function as external address/ data bus higher input/output pins. d08 to d15 in non-multiplex mode, these pins function as external data bus higher output pins. 99 100 1 2 1 to 4 p20 to p23 e (cmos/h) general purpose input/output ports. in external bus mode, pins for which the corresponding bit in the external address output control register (hacr) is 1 function as the general purpose input/output ports. a16 to a19 in multiplex mode, pins for which the corresponding bit in the external address output control register (hacr) is 0 function as the upper address output pins (a16 to a19) . a16 to a19 in non-multiplex mode, pins for which the corresponding bit in the external address output control register (hacr) is 0 function as the upper address output pins (a16 to a19) . 3 to 6 5 to 8 p24 to p27 e (cmos/h) general purpose input/output ports. in external bus mode, pins for which the corresponding bit in the external address output control register (hacr) is 1 function as the general purpose input/output ports. a20 to a23 in multiplex mode, pins for which the corresponding bit in the external address output control register (hacr) is 0 function as the upper address output pins (a20 to a23) . a20 to a23 in non-multiplex mode, pins for which the corresponding bit in the external address output control register (hacr) is 0 function as the upper address output pins (a20 to a23) . ppg0 to ppg3 ppg timer output pins.
mb90470 series 9 (continued) lqfp : fpt-100p-m05 package qfp : fpt-100p-m06 package pin no. pin name circuit type description lqfp qfp 79 p30 e (cmos/h) general purpose input/output port. a00 in non-multibus bus mode, this pin functions as an external address pin. ain0 8/16-bit up-down timer input pin. (ch0) 810 p31 e (cmos/h) general purpose input/output port. a01 in non-multibus bus mode, this pin functions as an external address pin. bin0 8/16-bit up-down timer input pin. (ch0) 10 12 p32 e (cmos/h) general purpose input/output port. a02 in non-multibus bus mode, this pin functions as an external address pin. zin0 8/16-bit up-down timer input pin. (ch0) 11 13 p33 e (cmos/h) general purpose input/output port. a03 in non-multibus bus mode, this pin functions as an external address pin. ain1 8/16-bit up-down timer input pin. (ch1) 12 14 p34 e (cmos/h) general purpose input/output port. a04 in non-multibus bus mode, this pin functions as an external address pin. bin1 8/16-bit up-down timer input pin. (ch1) 13 15 p35 e (cmos/h) general purpose input/output port. a05 in non-multibus bus mode, this pin functions as an external address pin. zin1 8/16-bit up-down timer input pin. (ch1) 14 15 16 17 p36, p37 e (cmos/h) general purpose input/output ports. a06, a07 in non-multibus bus mode, this pin functions as an external address pin. pwc0, pwc1 functions as pwc input pin. 16 18 p40 g (cmos/h) general purpose input/output port. a08 in non-multibus bus mode, this pin functions as an external address pin. sin2 single serial i/o input pin 17 19 p41 f (cmos) general purpose input/output port. a09 in non-multibus bus mode, this pin functions as an external address pin. sot2 single serial i/o output pin
mb90470 series 10 (continued) lqfp : fpt-100p-m05 package qfp : fpt-100p-m06 package pin no. pin name circuit type description lqfp qfp 18 20 p42 g (cmos/h) general purpose input/output port. a10 in non-multibus bus mode, this pin functions as an external address pin. sck2 single serial i/o clock input/output pin 19 20 21 22 p43, p44 f (cmos) general purpose input/output ports. a11, a12 in non-multibus bus mode, this pin functions as an external address pin. mt00, mt01 m pg input pins 22 24 p45 g (cmos/h) general purpose input/output ports. a13 in non-multibus bus mode, this pin functions as an external address pin. extc m pg input pin 23 24 25 26 p46, p47 f (cmos) general purpose input/output ports. a14, a15 in non-multibus bus mode, this pin functions as an external address pin. out4/out5 output compare event output pins 68 70 p50 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the ale pin ale in external bus mode, this pin functions as the address load enable signal (ale) pin 69 71 p51 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the rd pin. rd in external bus mode, this pin functions as the read strobe output (rd ) pin. 70 72 p52 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the wrl pin when the wre bit in the epcr register is set to 1. wrl in external bus mode, this pin functions as the lower data write strobe output (wrl ) pin. when the wre bit in the epcr register is set to 0,this pin functions as a general purpose input/output port. 71 73 p53 d (cmos) general purpose input/output port. in external bus mode with 16-bit bus width, this pin functions as the wrh pin when the wre bit in the epcr register is set to 1. wrh in external bus mode with 16-bit bus width, this pin functions as the higher data write strobe output (wrh ) pin. when the wre bit in the epcr register is set to 0,this pin functions as a general purpose input/output port.
mb90470 series 11 (continued) lqfp : fpt-100p-m05 package qfp : fpt-100p-m06 package pin no. pin name circuit type description lqfp qfp 72 74 p54 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the hrq pin when the hde bit in the epcr register is set to 1. hrq in external bus mode, this pin functions as the hold request input (hrq) pin. when the hde bit in the epcr register is set to 0,this pin functions as a general purpose input/output port. 73 75 p55 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the hak pin when the hde bit in the epcr register is set to 1. hak in external bus mode, this pin functions as the hold acknowl- edge output (hak ) pin. when the hde bit in the epcr register is set to 0,this pin functions as a general purpose input/output port. 74 76 p56 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the dry pin when the rye bit in the epcr register is set to 1. rdy in external bus mode, this pin functions as the external ready input (rdy) pin. when the rye bit in the epcr register is set to 0,this pin functions as a general purpose input/output port. 76 78 p57 d (cmos) general purpose input/output port. in external bus mode, this pin functions as the clk pin when the cke bit in the epcr register is set to 1. clk in external bus mode, this pin functions as the machine cycle clock output (clk) pin. when the cke bit in the epcr register is set to 0,this pin functions as a general purpose input/output port. 36 to 39 38 to 41 p60 to p63 h (cmos) general purpose input/output ports. an0 to an3 analog input pins. 41 to 44 43 to 46 p64 to p67 h (cmos) general purpose input/output ports. an4 to an7 analog input pins. 25 27 p70 g (cmos/h) general purpose input/output port. sin0 uart data input pin. 26 28 p71 f (cmos) general purpose input/output port. sot0 uart data output pin. 27 29 p72 g (cmos/h) general purpose input/output port. sck0 uart clock input pin. 28 30 p73 g (cmos/h) general purpose input/output port. tin0 16-bit reload timer event input pin. 29 31 p74 f (cmos) general purpose input/output port. tot0 16-bit reload timer output pin.
mb90470 series 12 (continued) lqfp : fpt-100p-m05 package qfp : fpt-100p-m06 package pin no. pin name circuit type description lqfp qfp 30 32 p75 g (cmos/h) general purpose input/output port. pwc2 pwc input pin. 31 33 p76 i (nmos/h) general purpose input/output port. scl i 2 c interface data input/output pin. during i 2 c interface operation, the port output should be set to high-z level. 32 34 p77 i (nmos/h) general purpose input/output port. sda i 2 c interface clock input/output pin. during i 2 c interface operation, the port output should be set to high-z level. 45 46 47 48 p80, p81 e (cmos/h) general purpose input/output ports. irq0, irq1 external interrupt input pins. 50 to 55 52 to 57 p82 to p87 e (cmos/h) general purpose input/output ports. irq2 to irq7 external interrupt input pins. 56 58 p90 e (cmos/h) general purpose input/output port. sin1 single serial i/o data input pin. cs0 chip select 0. 57 59 p91 d (cmos) general purpose input/output port. sot1 single serial i/o data output pin. cs1 chip select 1. 58 60 p92 e (cmos/h) general purpose input/output port. sck1 single serial i/o clock input/output pin. cs2 chip select 2. 59 61 p93 e (cmos/h) general purpose input/output port. frck in free run timer operation, this pin functions as the external clock input pin. adtg in a/d converter operation, this pin functions as the external trigger input pin. cs3 chip select 3. 60 62 p94 d (cmos) general purpose input/output port. ppg4 ppg timer output pin. 61 63 p95 d (cmos) general purpose input/output port. ppg5 ppg timer output pin. 62 64 p96 e (cmos/h) general purpose input/output port. in0 functions as input capture ch 0 trigger input.
mb90470 series 13 (continued) lqfp : fpt-100p-m05 package qfp : fpt-100p-m06 package notes : for use as a 3.3 v single supply device, apply the same voltage to the v cc 3 and v cc 5 power supply pins. for use with a dual power supply, apply the respective voltages to the v cc 3 and v cc 5 power supply pins. in use with a dual power supply, a total of 32 pins (p20/a16 to p27/a23/ppg3, p30/a00/ain0 to p37/ a07/pwc1, p40/a08/sin2 to p47/a15/out5 and p70/sin0 to p77/sda) can be used in a 5 v interface. note that all other pins must be used in 3 v interface. in use with a dual power supply, it is not possible to turn on only the 5 v or the 3 v power supply independently. always turn on both power supplies simultaneously. (it is recommended that the 3 v power to the mb90470 series be turned on first.) pin no. pin name circuit type description lqfp qfp 63 65 p97 e (cmos/h) general purpose input/output port. in1 functions as input capture ch 1 trigger input. 64 to 67 66 to 69 pa0 to pa3 d (cmos) general purpose input/output ports. out0 to out3 output compare event output pins. 33 35 av cc ? a/d converter power supply pin. 34 36 avrh ? a/d converter external reference power pin. 35 37 av ss ? a/d converter power supply pin. 47 to 49 49 to 51 md0 to md2 j (cmos/h) input pins for specifying operating mode. 82 84 v cc 3 ? 3.3 v 0.3 v power supply pin (v cc 3) . 21 23 v cc 5 ? 3.3 v 0.3 v/5.0 v 0.5 v dual power supply pin (v cc 5) . 9 40 79 11 42 81 v ss ? power supply input pins (gnd) .
mb90470 series 14 n i/o circuit types (continued) type circuit remarks a oscillator feedback resistance : x1,x0 1 m w approx. x1a,x0a 10 m w approx. includes standby control b hysteresis with pull-up resistance input resistance 50 k w approx. c includes input pull-up resistance control cmos level input/output resistance : 50 k w approx. d cmos level input/output e hysteresis input cmos level input/output x1, x1a x0, x0a standby control signal hys ctl cmos cmos cmos
mb90470 series 15 (continued) type circuit remarks f cmos level input/output includes open drain control g cmos level output hysteresis input includes open drain control h cmos level input/output analog input i hysteresis input n-ch open drain output j flash model cmos level input includes high voltage control for flash test mask version hysteresis input port cmos open drain control signal hys open drain control signal cmos analog input hys digital output mode input control signal spreading resistance (flash model) hys (mask version)
mb90470 series 16 n handling devices (1) strictly observe maximum rated voltages (prevent latchup) when cmos integrated circuit devices are subjected to applied voltages higher than v cc at input and output pins other than medium- and high-withstand voltage pins, or to voltages lower than v ss , or when voltages in excess of rated levels are applied between v cc and v ss , a phenomenon known as latchup can occur. in a latchup condition, supply current can increase dramatically and may destroy semiconductor elements. in using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings. also care must be taken when power to analog systems is switched on or off, to ensure that the analog power supply (av cc , avrh) and analog input do not exceed the digital power supply (v cc ) . (2) treatment of unused pins if unused input pins are left open, abnormal operation or latchup may cause permanent damage to the semiconductor. any such pins should be pulled up or pulled down through resistance of at least 2 k w . also any unused input/output pins should be left open in output status, or if set to input status should be treated in the same way as input pins. (3) precautions for use of external clock signals even when an external clock is used, a stabilization period is required following a power-on reset or release from sub clock mode or stop mode. also, when an external clock is used 20 mhz should be used as a guideline for an upper frequency limit. the following figure shows a sample use of external clock signals. (4) power supply pins when using multiple v cc /v ss sources, always make sure to design devices with external connections of all power supply pins to supply or ground elements, in order to prevent latchup, reduce unwanted radiation, and prevent abnormal strobe signal operation due to rise in ground level, as well as to maintain total rated output current. in addition, care must be given to connecting the v cc and v ss pins of this device to a current source with as little impedance as possible. it is recommended that a bypass capacitor of 1.0 m f be connected between v cc and v ss as close to the pins as possible. (5) crystal oscillator circuits abnormal operation of this device can result from noise in the proximity of the x0/x1 and x0a/x1a pins. for stable operation, it is strongly recommended that the printed circuit artwork provide capacitors placed as close as possible between the x0/x1, x0a/x1a and crystal oscillator (or ceramic oscillator) as well as ground, and be wired so as to avoid crossing other wiring wherever possible. x0 x1 open
mb90470 series 17 (6) precautions for use of external oscillators (crystals) the target value for the upper limit of oscillator (crystals) frequencies should be 20 mhz. also, when operating at internal frequencies of 16 mhz, the pll multiplier should be used. (7) proper power-on/off sequence the a/d converter power (av cc , avrh) and analog input (an0 to an7) must be turned on after the digital power supply (v cc ) is turned on. the a/d converter power (av cc , avrh) and analog input (an0 to an7) must be shut off before the digital power supply (v cc ) is shut off. care should be taken that avrh does not exceed av cc . even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed av cc . note : v cc = v cc 3 = v cc 5 (8) treatment of a/d converter power supply pins even if the a/d converter is not used, pins should be connected so that av cc = avrh = v cc , and av ss = v ss . (9) power-on procedures in order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise during power-on should be attained within 50 m s (0.2 v to 2.7 v) . (10) stable power supply even within the operating range of the v cc supply voltage, rapid changes in supply voltage may cause abnormal operation. as a basis for stable operation, it is recommended that voltage variation be restricted in order to limit v cc ripple fluctuations (p-p values) to 10 % at commercial frequencies of 50 hz to 60 hz, and transient fluctuations to 0.1 v/ms at instantaneous points such as power switching. (11) precautions for use of two power supplies the mb90470 series usually uses the 3-v power supply as the main power source. with v cc 3 = 3 v and v cc 5 = 5 v, however, it can interface with p20/a16 to p27/a23/ppg3, p30/a00/ain0 to p37/a07/pwc1, p40/a08/sin2 to p47/a15/out5, p70/sin0 to p77/sda for the 5-v power supply separetely from the 3-v power supply at all operation mode. (caution) the analog power supply for the a/d converter (av cc , av ss etc.) can only operate with the 3 v system. (12) crystal oscillator circuits during power-saving operation when the power supply is lower than 2.0 v, the external crystal oscillator may not operate even when power is on. for this reason, the use of an external clock signal is recommended. (13) caution : low-voltage flash models (2.4 v to 3.6 v/10 mhz) do not have security functions (14) treatment of unused input pins n.c. (internally connected) pins should always be left open. (15) when the dual-supply mb90470 series is used as a 1-supply device, use connections so that x0a = = = = v ss , and x1a = = = = open.
mb90470 series 18 (16) for serial writing to flash memory, always make sure that the operating voltage v cc is between 3.13 v and 3.6 v. for normal writing to flash memory, always make sure that the operating voltage v cc is between 3.0 v and 3.6 v. (17) caution on operations during pll clock mode if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed.
mb90470 series 19 n block diagram p00 to p07 (8 pins) : input pull-up resistance setting register provided. p10 to p17 (8 pins) : input pull-up resistance setting register provided. p40 to p47 (8 pins) : open drain setting register provided. p70 to p75 (6 pins) : open drain setting register provided. p76, p77 (2 pins) : open drain note : in the above diagram, i/o ports are shown sharing pin numbers with the built-in function blocks. however pins may not be used as i/o ports when they are in use as pins for build-in function modules. ram clock control circuit 888888888 p00 p07 p10 p17 p20 p27 p30 p37 p40 p47 p50 p57 p60 p67 p70 p77 p80 p87 ~ ~ ~ ~ ~ ~ ~ ~ ~ rom m dma communication prescaler uart i/o expansion serial interface 2 channels a/d converter (10-bit) in0, in1 out0, out1, out2, out3, out4, out5 8 p90 p97 ~ cs0, cs1, cs2, cs3 4 pa0 pa3 ~ 8 2 x0, x1, rst x0a, x1a md2, md1, md0 sin0 sot0 sck0 sin1, sin2 sot1, sot 2 sck1, sck2 av cc avrh av ss adtg an0 to an7 ain0, ain1 bin0, bin1 zin0, zin1 pwc0 pwc1 pwc2 ppg0, ppg1 ppg2, ppg3 ppg4, ppg5 irq0 to irq7 8 extc mt00 mt01 tin0 tot0 scl sda m pg chip select 16-bit reload timer i 2 c interface external interrupt i/o ports input/output timer 16-bit input capture 2 16-bit output compare 6 16-bit free-run timer cpu fmc-16lx series core interrupt controller 8/16-bit ppg 8/16-bit up/down counter 16-bit pwc 3 channels f 2 mc-16lx bus
mb90470 series 20 n memory map * : in models where address 2# coincides with 004000 h , there is no external area. the image of ff bank rom is reflected in the top of the 00 bank, for greater efficiency in using the c compiler for small models. the lower 16-bit address on the ff bank is the same as the lower 16-bit address on the 00 bank, so that it is possible to reference tables in rom without using the pointer for a far specification. for example, when accessing 00c000 h , it is actually the content of rom at ffc000 h that is accessed. here, because the rom area on the ff bank exceeds 48 kb, it is not possible to view the entire area in the image on the 00 bank. therefore, the image from ff4000 h to ffffff h is visible on the 00 bank, and ff0000 h to ff3fff h is visible only on the ff bank. model address 1# address 2# mb90473 fe0000 h 002900 h mb90474 fc0000 h 004000 h mb90477/478 fc0000 h 002100 h mb90f474 fc0000 h 004000 h mb90v470 (fc0000 h ) 004000 h ffffff h address 1# address 2# 010000 h 004000 h 000100 h 0000d0 h 000000 h : internal : external : access not available ram ram single chip internal rom external bus rom area rom area rom area ff bank image rom area ff bank image external rom external bus peripheral peripheral peripheral ram register register register *
mb90470 series 21 n f 2 mc-16l cpu programming model ? special purpose registers ? general purpose registers ? processor status ah al dpr pcb dtb usb ssb adb direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register 8 bit 16 bit 32 bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16 bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70
mb90470 series 22 n i / o map (continued) address register name symbol access resource name default 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx 07 h port 7 data register pdr7 r/w port 7 1 1xxxxxx 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx 0a h port a data register pdra r/w port a - - - - xxxx 0b h port 3 timer input enable register udre r/w up/down timer input control xx 0 0 0 0 0 0 0c h interrupt/dtp enable register enir r/w dtp/external interrupt 0 0 0 0 0 0 0 0 0d h interrupt/dtp enable register eirr r/w 0 0 0 0 0 0 0 0 0e h demand level setting register elvr r/w 0 0 0 0 0 0 0 0 0f h demand level setting register r/w 0 0 0 0 0 0 0 0 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 17 h port 7 direction register ddr7 r/w port 7 - - 0 0 0 0 0 0 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 19 h port 9 direction register ddr9 r/w port 9 0 0 0 0 0 0 0 0 1a h port a direction register ddra r/w port a - - - - 0 0 0 0 1b h port 4 pin register odr4 r/w port 4 (od control) 0 0 0 0 0 0 0 0 1c h port 0 resistance register rdr0 r/w port 0 (pull-up) 0 0 0 0 0 0 0 0 1d h port 1 resistance register rdr1 r/w port 1 (pull-up) 0 0 0 0 0 0 0 0 1e h port 7 pin register odr7 r/w port 7 (od control) - - 0 0 0 0 0 0 1f h analog input enable register ader r/w port 5, a/d 1 1 1 1 1 1 1 1
mb90470 series 23 (continued) address register name symbol access resource name default 20 h serial mode register 0 smr0 r/w uart0 0 0 0 0 0 x 0 0 21 h serial control register 0 scr0 r/w 0 0 0 0 0 1 0 0 22 h serial input register/ serial output register sidr/ sodr0 r/w xxxxxxxx 23 h serial status register ssr0 r/w 0 0 0 0 1 0 0 0 24 h reserved 25 h clock divider control register cdcr r/w communication prescaler (uart) 0 0 - - 0 0 0 0 26 h serial mode control status register 0 smcs0 r/w sci1 (ch0) - - - - 0 0 0 0 27 h serial mode control status register 0 smcs0 r/w 0 0 0 0 0 0 1 0 28 h serial data register sdr0 r/w xxxxxxxx 29 h clock divider control register sdcr0 r/w communication prescaler (sci0) 0 - - - 0 0 0 0 2a h serial mode control status register 1 smcs1 r/w sci2 (ch1) - - - - 0 0 0 0 2b h serial mode control status register 1 smcs1 r/w 0 0 0 0 0 0 1 0 2c h serial data register sdr1 r/w xxxxxxxx 2d h clock divider control register sdcr1 r/w communication prescaler (sci1) 0 - - - 0 0 0 0 2e h ppg reload register l (ch0) prll0 r/w 8/16-bit ppg (ch0-ch5) xxxxxxxx 2f h ppg reload register h (ch0) prlh0 r/w xxxxxxxx 30 h ppg reload register l (ch1) prll1 r/w xxxxxxxx 31 h ppg reload register h (ch1) prlh1 r/w xxxxxxxx 32 h ppg reload register l (ch2) prll2 r/w xxxxxxxx 33 h ppg reload register h (ch2) prlh2 r/w xxxxxxxx 34 h ppg reload register l (ch3) prll3 r/w xxxxxxxx 35 h ppg reload register h (ch3) prlh3 r/w xxxxxxxx 36 h ppg reload register l (ch4) prll4 r/w xxxxxxxx 37 h ppg reload register h (ch4) prlh4 r/w xxxxxxxx 38 h ppg reload register l (ch5) prll5 r/w xxxxxxxx 39 h ppg reload register h (ch5) prlh5 r/w xxxxxxxx 3a h ppg0 operating mode control register ppgc0 r/w 0 x 0 0 0xx 1 3b h ppg1 operating mode control register ppgc1 r/w 0 x 0 0 0 0 0 1 3c h ppg2 operating mode control register ppgc2 r/w 0 x 0 0 0xx 1 3d h ppg3 operating mode control register ppgc3 r/w 0 x 0 0 0 0 0 1 3e h ppg4 operating mode control register ppgc4 r/w 0 x 0 0 0xx 1 3f h ppg5 operating mode control register ppgc5 r/w 0 x 0 0 0 0 0 1 40 h ppg0, 1 output control register ppg01 r/w 8/16-bit ppg 0 0 0 0 0 0 0 0
mb90470 series 24 (continued) address register name symbol access resource name default 41 h reserved 42 h ppg2, 3 output control register ppg23 r/w 8/16-bit ppg 0 0 0 0 0 0 0 0 43 h reserved 44 h ppg4, 5 output control register ppg45 r/w 8/16-bit ppg 0 0 0 0 0 0 0 0 45 h reserved 46 h control status register adcs1 r/w a/d converter 0 0 0 0 0 0 0 0 47 h adcs2 r/w 0 0 0 0 0 0 0 0 48 h data register adcr1 r xxxxxxxx 49 h adcr2 r 0 0 0 0 0 xxx 4a h output compare register (ch0) low occp0 r/w 16-bit output timer output compare (ch0-ch5) xxxxxxxx 4b h output compare register (ch0) high xxxxxxxx 4c h output compare register (ch1) low occp1 r/w xxxxxxxx 4d h output compare register (ch1) high xxxxxxxx 4e h output compare register (ch2) low occp2 r/w xxxxxxxx 4f h output compare register (ch2) high xxxxxxxx 50 h output compare register (ch3) low occp3 r/w xxxxxxxx 51 h output compare register (ch3) high xxxxxxxx 52 h output compare register (ch4) low occp4 r/w xxxxxxxx 53 h output compare register (ch4) high xxxxxxxx 54 h output compare register (ch5) low occp5 r/w xxxxxxxx 55 h output compare register (ch5) high xxxxxxxx 56 h output compare control register (ch0) ocs0 r/w 0 0 0 0 - - 0 0 57 h output compare control register (ch1) ocs1 r/w - - - 0 0 0 0 0 58 h output compare control register (ch2) ocs2 r/w 0 0 0 0 - - 0 0 59 h output compare control register (ch3) ocs3 r/w ? - - - 0 0 0 0 0 5a h output compare control register (ch4) ocs4 r/w 16-bit output timer ocu (ch4, 5) 0 0 0 0 - - 0 0 5b h output compare control register (ch5) ocs5 r/w - - - 0 0 0 0 0 5c h input capture register (ch0) low ipcp0 r 16-bit output timer input capture (ch0, 1) xxxxxxxx 5d h input capture register (ch0) high r xxxxxxxx 5e h input capture register (ch1) low ipcp1 r xxxxxxxx 5f h input capture register (ch1) high r xxxxxxxx 60 h input capture control register ics01 r/w 0 0 0 0 0 0 0 0 61 h reserved
mb90470 series 25 (continued) address register name symbol access resource name default 62 h timer data register low tcdt r/w 16-bit output timer free run timer 0 0 0 0 0 0 0 0 63 h timer data register high tcdt r/w 0 0 0 0 0 0 0 0 64 h timer control status register tccs r/w 0 0 0 0 0 0 0 0 65 h timer control status register tccs r/w 0 - - 0 0 0 0 0 66 h compare clear register low cpclr r/w xxxxxxxx 67 h compare clear register high xxxxxxxx 68 h up down count register ch0 udcr0 r 8/16-bit up-down timer-counter 0 0 0 0 0 0 0 0 69 h up down count register ch1 udcr1 r 0 0 0 0 0 0 0 0 6a h reload compare register ch0 rcr0 w 0 0 0 0 0 0 0 0 6b h reload compare register ch1 rcr1 w 0 0 0 0 0 0 0 0 6c h counter control register low ch0 ccrl0 r/w 0 x 0 0 x 0 0 0 6d h counter control register high ch0 ccrh0 r/w 0 0 0 0 0 0 0 0 6e h reserved 6f h rom mirror function select register romm w rom mirror function - - - - - - - 1 70 h counter control register low ch1 ccrl1 r/w 8/16-bit up-down timer-counter 0 x 0 0 x 0 0 0 71 h counter control register high ch1 ccrh1 r/w - 0 0 0 0 0 0 0 72 h count status register ch0 csr0 r/w 0 0 0 0 0 0 0 0 73 h reserved 74 h count status register ch1 csr1 r/w 8/16-bit udc 0 0 0 0 0 0 0 0 75 h reserved 76 h pwc0 control status register pwcsr0 r/w 16-bit pwc timer (ch0) 0 0 0 0 0 0 0 0 77 h 0 0 0 0 0 0 0 x 78 h pwc0 data buffer register pwcr0 r/w 0 0 0 0 0 0 0 0 79 h 0 0 0 0 0 0 0 0 7a h pwc1 control status register pwcsr1 r/w 16-bit pwc timer (ch1) 0 0 0 0 0 0 0 0 7b h 0 0 0 0 0 0 0 x 7c h pwc1 data buffer register pwcr1 r/w 0 0 0 0 0 0 0 0 7d h 0 0 0 0 0 0 0 0 7e h pwc2 control status register pwcsr2 r/w 16-bit pwc timer (ch2) 0 0 0 0 0 0 0 0 7f h 0 0 0 0 0 0 0 x 80 h pwc2 data buffer register pwcr2 r/w 0 0 0 0 0 0 0 0 81 h 0 0 0 0 0 0 0 0 82 h pwc0 division ratio register divr0 r/w pwc (ch0) - - - - - - 0 0 83 h reserved 84 h pwc1 division ratio register divr1 r/w pwc (ch1) - - - - - - 0 0 85 h reserved
mb90470 series 26 (continued) address register name symbol access resource name default 86 h pwc2 division ratio register divr2 r/w pwc (ch2) - - - - - - 0 0 87 h reserved 88 h i 2 c bus status register ibsr r i 2 c functions 0 0 0 0 0 0 0 0 89 h i 2 c bus control register ibcr r/w 0 0 0 0 0 0 0 0 8a h i 2 c bus clock select register iccr r/w - - 0xxxxx 8b h i 2 c bus address register iadr r/w - xxxxxxx 8c h i 2 c bus data register idar r/w xxxxxxxx 8d h reserved 8e h m pg control register pgcsr r/w m pg 0 0 0 0 0 - - - 8f h to 9b h prohibited 9c h m dma status register dsrl r/w m dma 0 0 0 0 0 0 0 0 9d h m dma status register dsrh r/w m dma 0 0 0 0 0 0 0 0 9e h program address detection control status resister pacsr r/w address match detection function 0 0 0 0 0 0 0 0 9f h delay interrupt source generate/ release register dirr r/w delay interrupt generator module - - - - - - - - 0 a0 h low power mode register lpmcr r/w low power modes 0 0 0 1 1 0 0 0 a1 h clock select register ckscr r/w low power modes 1 1 1 1 1 1 0 0 a2 h , a3 h reserved a4 h m dma stop status register dssr r/w m dma 0 0 0 0 0 0 0 0 a5 h auto ready function select register arsr w external pins 0 0 1 1 - - 0 0 a6 h external address output control register hacr w external pins 0 0 0 0 0 0 0 0 a7 h bus control signal control register epcr w external pins 1 0 0 0 * 1 0 - a8 h watchdog control register wdtc r/w watchdog timer xxxxx 1 1 1 a9 h time base timer control register tbtc r/w time base timer 1 x x 0 0 1 0 0 aa h watch timer control register wtc r/w watch timer 1 0 0 0 1 0 0 0 ab h reserved ac h m dma control register derl r/w m dma 0 0 0 0 0 0 0 0 ad h m dma control register derh r/w m dma 0 0 0 0 0 0 0 0 ae h flash memory control status register fmcr r/w flash memory interface 0 0 0 x 0 0 0 0 af h prohibited b0 h interrupt control register 00 icr00 r/w ? xxxx 0 1 1 1 b1 h interrupt control register 01 icr01 r/w ? xxxx 0 1 1 1 b2 h interrupt control register 02 icr02 r/w ? xxxx 0 1 1 1 b3 h interrupt control register 03 icr03 r/w ? xxxx 0 1 1 1
mb90470 series 27 (continued) address register name symbol access resource name default b4 h interrupt control register 04 icr04 r/w ? xxxx 0 1 1 1 b5 h interrupt control register 05 icr05 r/w ? xxxx 0 1 1 1 b6 h interrupt control register 06 icr06 r/w ? xxxx 0 1 1 1 b7 h interrupt control register 07 icr07 r/w ? xxxx 0 1 1 1 b8 h interrupt control register 08 icr08 r/w ? xxxx 0 1 1 1 b9 h interrupt control register 09 icr09 r/w ? xxxx 0 1 1 1 ba h interrupt control register 10 icr10 r/w ? xxxx 0 1 1 1 bb h interrupt control register 11 icr11 r/w ? xxxx 0 1 1 1 bc h interrupt control register 12 icr12 r/w ? xxxx 0 1 1 1 bd h interrupt control register 13 icr13 r/w ? xxxx 0 1 1 1 be h interrupt control register 14 icr14 r/w ? xxxx 0 1 1 1 bf h interrupt control register 15 icr15 r/w ? xxxx 0 1 1 1 c0 h chip select mask register 0 cmr0 r/w chip select functions 0 0 0 0 1 1 1 1 c1 h chip select area register 0 car0 r/w ? 1 1 1 1 1 1 1 1 c2 h chip select mask register 1 cmr1 r/w ? 0 0 0 0 1 1 1 1 c3 h chip select area register 1 car1 r/w ? 1 1 1 1 1 1 1 1 c4 h chip select mask register 2 cmr2 r/w ? 0 0 0 0 1 1 1 1 c5 h chip select area register 2 car2 r/w ? 1 1 1 1 1 1 1 1 c6 h chip select mask register 3 cmr3 r/w ? 0 0 0 0 1 1 1 1 c7 h chip select area register 3 car3 r/w ? 1 1 1 1 1 1 1 1 c8 h chip select control register cscr r/w ? - - - - 0 0 0 * c9 h chip select control active level register calr r/w ? - - - - 0 0 0 0 ca h timer control status registers tmcsr r/w 16-bit reload timer 0 0 0 0 0 0 0 0 cb h - - - - 0 0 0 0 cc h 16-bit timer register 16-bit reload register tmr/ tmrlr r/w xxxxxxxx cd h ce h , cf h reserved d0 h to ff h external area 100 h to # h ram area 1ff0 program address detection resister0 (low order address) padr0 r/w address match detection function xxxxxxxx 1ff1 program address detection resister0 (middle order address) 1ff2 program address detection resister0 (high order address)
mb90470 series 28 (continued) interrupt symbols : r/w : read/write enabled r : read only w : write only default value symbols : 0 : this bit initialized to 0 1 : this bit initialized to 1 * : this bit initialized to 0 or 1 x : default value undefined - : this bit is not used. address register name symbol access resource name default 1ff3 program address detection resister1 (low order address) padr1 r/w address match detection function xxxxxxxx 1ff4 program address detection resister1 (middle order address) 1ff5 program address detection resister1 (high order address)
mb90470 series 29 n interrupt sources, interrupt vectors & interrupt control registers (continued) interrupt source ei 2 os support m m m m dma channel no. interrupt vector interrupt control register no. address no. address reset ?? #08 ffffdc h ?? int9 instruction ?? #09 ffffd8 h ?? exception ?? #10 ffffd4 h ?? int0 0 #11 ffffd0 h icr00 0000b0 h int1 #12 ffffcc h int2 #13 ffffc8 h icr01 0000b1 h int3 #14 ffffc4 h int4 #15 ffffc0 h icr02 0000b2 h int5 #16 ffffbc h int6 #17 ffffb8 h icr03 0000b3 h int7 #18 ffffb4 h pwc1 #19 ffffb0 h icr04 0000b4 h pwc2 #20 ffffac h pwc0 1 #21 ffffa8 h icr05 0000b5 h ppg0/ppg1 counter borrow 2 #22 ffffa4 h ppg2/ppg3 counter borrow 3 #23 ffffa0 h icr06 0000b6 h ppg4/ppg5 counter borrow 4 #24 ffff9c h 8/16-bit up/down counter timer compare/ underflow /overflow/ amp down inversion (ch0, 1) #25 ffff98 h icr07 0000b7 h input capture (ch0) load 5 #26 ffff94 h input capture (ch1) load 6 #27 ffff90 h icr08 0000b8 h output compare (ch0) match 8 #28 ffff8c h output compare (ch1) match 9 #29 ffff88 h icr09 0000b9 h output compare (ch2) match 10 #30 ffff84 h output compare (ch3) match #31 ffff80 h icr10 0000ba h output compare (ch4) match #32 ffff7c h output compare (ch5) match #33 ffff78 h icr11 0000bb h uart send end 11 #34 ffff74 h 16-bit free run timer/ 16-bit reload timer overflow 12 #35 ffff70 h icr12 0000bc h uart receive end 7 #36 ffff6c h
mb90470 series 30 (continued) : interrupt request flag cleared by the interrupt clear signal. the stop request is available. : interrupt request flag cleared by the interrupt clear signal. : interrupt request flag not cleared by the interrupt clear signal. * : note that flash write/erase cannot be used at the same time as the time base timer or watch timer. note : if two or more interrupt sources have the same interrupt number, the resource will clear both interrupt request flags at the ei 2 os/dmac interrupt clear signal. thus when ei 2 os/ m dma function of two sources is used, the other interrupt function cannot be used. the interrupt request enable bit of the corresponding resource should be set to 0 for software polling processing. maximum assured operation frequency of m dma is 16 mhz. interrupt source ei 2 os support m m m m dma channel no. interrupt vector interrupt control register no. address no. address sio1 13 #37 ffff68 h icr13 0000bd h sio2 14 #38 ffff64 h i 2 c interface #39 ffff60 h icr14 0000be h a/d 15 #40 ffff5c h flash write/erase, time base timer, watch timer* #41 ffff58 h icr15 0000bf h delay interrupt generator module #42 ffff54 h
mb90470 series 31 n peripheral resources 1. i/o ports the i/o ports output data from the cpu to the i/o pins, and also load signals input at the i/o pins into the cpu, according to the port register (pdr) . the ports can also control the input/output direction of the i/o pins in bit units according to the port direction register (ddr) . the mb90470 series has 82 input/output pins and two open drain output pins. ports 0 through a are input/output ports, and port 76, and 77 are the open drain ports. (1) port registers * : input/output port read/write operations are somewhat different than reading and writing to memory, and operate as follows. input mode read : reads the signal level of the corresponding pin. write : writes to the output latch. output mode read : reads the value of the data register latch. write : value is output to the corresponding pin. pdr0 default value access address : 000000 h undefined r/w* pdr1 address : 000001 h undefined r/w* pdr2 address : 000002 h undefined r/w* pdr3 address : 000003 h undefined r/w* pdr4 address : 000004 h undefined r/w* pdr5 address : 000005 h undefined r/w* pdr6 address : 000006 h undefined r/w* pdr7 address : 000007 h 11xxxxxx r/w* pdr8 address : 000008 h undefined r/w* pdr9 address : 000009 h undefined r/w* pdra address : 00000a h undefined r/w* 7654 321 0 p06 p07 p05 p04 p03 p02 p01 p00 7654 321 0 p16 p17 p15 p14 p13 p12 p11 p10 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p36 p37 p35 p34 p33 p32 p31 p30 7654 321 0 p46 p47 p45 p44 p43 p42 p41 p40 7654 321 0 p56 p57 p55 p54 p53 p52 p51 p50 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 p76 p77 p75 p74 p73 p72 p71 p70 7654 321 0 p86 p87 p85 p84 p83 p82 p81 p80 7654 321 0 p96 p97 p95 p94 p93 p92 p91 p90 7654 321 0 ? ??? pa3 pa2 pa1 pa0
mb90470 series 32 (2) port direction registers ? when a pin is functioning as a port, the corresponding pin control setting is as follows : 0 : input mode 1 : output mode the register value is 0 at reset. ? port 76, 77 these ports do not have ddr registers. data at these pins is always valid, so that when p76, p77 are used as i 2 c pins the pdr value should be 1. (the i 2 c functions should be stopped, when these pins are used as p76,p77 .) these ports have open drain configuration. if they are used as input ports, the output transistor is turned off, so that the output data register must be set to 1 and pull-up resistance applied. note : if these registers are accessed using read-modify-write instructions (such as bit set instructions) ,the bit that is the object of the instruction will be set to the specified value but for other bits the value of the corresponding output register will be rewritten to the input value of the pin at that time. for this reason when a pin used for input is switched to output, first write the desired value to the pdr register, then set the ddr register to switch the pin direction. ddr0 default value access address : 000010 h 00000000 r/w ddr1 address : 000011 h 00000000 r/w ddr2 address : 000012 h 00000000 r/w ddr3 address : 000013 h 00000000 r/w ddr4 address : 000014 h 00000000 r/w ddr5 address : 000015 h 00000000 r/w ddr6 address : 000016 h 00000000 r/w ddr7 address : 000017 h 00000000 r/w ddr8 address : 000018 h 00000000 r/w ddr9 address : 000019 h 00000000 r/w ddra address : 00001a h - - - - 0000 r/w 7654 321 0 d06 d07 d05 d04 d03 d02 d01 d 00 7654 321 0 d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 d26 d27 d25 d24 d23 d22 d21 d20 7654 321 0 d36 d37 d35 d34 d33 d32 d31 d30 7654 321 0 d46 d47 d45 d44 d43 d42 d41 d40 7654 321 0 d56 d57 d55 d54 d53 d52 d51 d50 7654 321 0 d66 d67 d65 d64 d63 d62 d61 d60 7654 321 0 ? ? d75 d74 d73 d72 d71 d70 7654 321 0 d86 d87 d85 d84 d83 d82 d81 d80 7654 321 0 d96 d97 d95 d94 d93 d92 d91 d90 7654 321 0 ? ??? da3 da2 da1 da0
mb90470 series 33 (3) input resistance registers these registers control pull-up resistance in input mode. 0 : no pull-up resistance in input mode. 1 : pull-up resistance applied in input mode. in output mode, the setting has no significance (no pull-up resistance) . the direction registers (ddr) control switching between input and output modes. in stop mode (spl = 1) pull-up resistance is removed (high impedance) . when an external bus is used, this function is prohibited and no values should be written to this register. (4) output pin registers these registers control open drain operation in output mode. 0 : operates as standard output port in output mode. 1 : operates as open drain port in output mode. in input mode, the setting has no significance (high-z output) . the direction registers (ddr) control switching between input and output modes. when an external bus is used, this function is prohibited and no values should be written to this register. (5) analog input enable register this register controls the port 6 pins as follows. 0 : port input/output mode. 1 : analog input mode. the register value is 1 at reset. (6) up-down timer input enable mode this register controls the port 3 pins as follows. 0 : port input mode 1 : up-down timer input mode. the register value is 0 at reset. in the mb90470 series, the pin functions are as follows : ude0 : p30/ain0, ude1 : p31/bin0, ude2 : p32/ zin0, ude3 : p33/ain1, ude4 : p34/bin1, ude5 : p35/zin1 rdr0 default value access address : 00001c h 00000000 r/w rdr1 address : 00001d h 00000000 r/w 7654 321 0 rd06 rd07 rd05 rd04 rd03 rd02 rd01 rd00 7654 321 0 rd16 rd17 rd15 rd14 rd13 rd12 rd11 rd10 odr7 default value access address : 00001e h 00000000 r/w odr4 address : 00001b h 00000000 r/w 7654 321 0 ? ? od75 od74 od73 od72 od71 od70 7654 321 0 od46 od47 od45 od44 od43 od42 od41 od40 ader default value access address : 00001f h 11111111 r/w 7654 321 0 ade6 ade7 ade5 ade4 ade3 ade2 ade1 ade0 uder default value access address : 00000b h xx000000 r/w 7654 321 0 ? ? ude5 ude4 ude3 ude2 ude1 ude0
mb90470 series 34 2. uart the uart is a serial i/o port for asynchronous (start-stop synchronized) communication or clk synchronized communication. ? full duplex double buffer ? asynchronous (start-stop synchronized) and clk synchronized (no start bit or stop bit) operation ? supports multi-processor modes ? built-in dedicated baud rate generator asynchronous operation : 76923/38461/19230/9615/500 k/250 kbps clk synchronized : 16 m/8 m/4 m/2 m/1 m/500 k ? baud rate can be set independently from external clock ? can use internal clock feed from ppg1. ? data length : 7 bits (asynchronous normal mode only) or 8 bits ? master-slave communication functions (in multi-processor mode) : allows 1 (master) -to-n (slave) communications ? error detection functions (parity, framing, overrun) ? nrz-encoded transfer signal ? dmac support (receiving/sending)
mb90470 series 35 (1) register list serial mode register (smr) serial control register (scr) serial input/output register (sidr/sodr) serial data register (ssr) communication prescaler control register (cdcr) address : 000020 h default value address : 000021 h default value address : 000022 h default value address : 000023 h default value address : 000025 h default value smr ? cdcr scr 15 0 sidr (r)/sodr (w) ssr 87 8 bit 8 bit (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( x ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 md0 (r/w) ( 0 ) md1 cs2 cs1 cs0 reserved scke soe (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( w ) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 p (r/w) ( 0 ) pen sbl cl a/d rec rxe txe (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ore ( r ) ( 0 ) pe fre rdrf tdre bds rie tie (r/w) ( 0 ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 srst (r/w) ( 0 ) md ?? div3 div2 div1 div0
mb90470 series 36 (2) block diagram md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a/d rec rex txe pe ore fre rdrf tdre bds rie tie f 2 mc-16lx bus sidr smr register scr register ssr register sodr sot0 sck0 sending interrupt (to cpu) tx clock rx clock receiving control circuits sending control circuits start bit detect circuit send start circuit receiving bit counter sending bit counter receiving parity counter receiving status judgement circuit sending parity counter receiving shifter sending shifter receiving interrupt (to cpu) sin0 clock select circuit control signal dedicated baud rate generator ppg1 (internal connection) external clock receiving control circuit dmac receiving error transmission signal (to cpu) sending control circuit control signal
mb90470 series 37 3. expanded i/o serial interface the expended i/o serial interface is a serial i/o interface in 8-bit 1 channel configuration allowing clock synchronized data transmission. the interface has two serial i/o operating modes. ? internal shift clock mode : data transfer is synchronized with an internal clock. ? external shift clock mode : data transfer is synchronized with a clock input from an external pin (sck) . this mode allows the external clock pin (sck) to be shared with a general purpose port that can transfer data according to cpu instructions. (1) register list serial mode control status register (smcs) serial data register (sdr) communication prescaler control register (sdcr0, sdcr1) initial value address : 000027 h 00002b h 0 0 0 0 0 0 1 0 b initial value address : 000026 h 00002a h - - - - 0 0 0 0 b initial value address : 000028 h 00002c h xxxxxxxx b initial value address : 000029 h 00002d h 0 - - - 0000 b 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 7654 321 0 ? ??? mode bds soe scoe (r/w) (r/w) (r/w) (r/w) ( ? ) ( ? ) ( ? ) ( ? ) 7654 321 0 d6 d7 d5 d4 d3 d2 d1 d0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ( ? )( ? )( ? ) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 ? (r/w) md ?? div3 div2 div1 div0
mb90470 series 38 (2) block diagram sin1, 2 sot1, 2 sck1, 2 internal clock smd2 smd1 smd0 sie sir busy stop strt mode bds 21 0 soe scoe internal data bus internal data bus sdr (serial data register) control circuit shift clock counter (msb first) d0 to d7 d7 to d0 (lsb first) select transfer direction interrupt request default value read write
mb90470 series 39 4. 8/10-bit a/d converter the a/d converter converts analog input voltages into digital values, and provides the following features : ? conversion time : minimum 4.9 m s per channel (at 98 machine cycles/machine clock 20 mhz, including sampling time) ? sampling time : minimum 3.0 m s per channel (at 60 machine cycles/machine clock 20 mhz) ? uses rc sequential comparison conversion with sample & hold circuit. ? selection of 8- or 10-bit resolution ? analog input from 8 channels, by program selection single conversion mode : convert 1 selected channel scan conversion mode : convert multiple consecutive channels. select up to 8 channels by program selection. continuous conversion mode : convert specified channel continuously. stop conversion mode : convert one channel, pause and stand by until the next start. (simultaneous conversion start available.) ? at the end of a/d conversion, an a/d conversion end interrupt request can be sent to the cpu. this interrupt request can start the m dma and transfer the conversion data to memory, making it ideal for continuous processing. ? start sources include selection of software, external trigger (falling edge) , or timer (rising edge) . (1) register list adcs2, adcs1 (control status registers) adcr2, adcr1 (data registers) adcs1 address : 000046 h ? default value ? bit attributes adcs2 bit address : 000047 h ? default value ? bit attributes adcr1 bit address : 000048 h ? default value ? bit attributes adcr2 bit address : 000049 h ? default value ? bit attributes 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 7654 3210 md0 0 r/w md1 ans2 ans1 ans0 ane2 ane1 ane0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 w 0 r/w 15 14 13 12 11 10 9 8 int 0 r/w busy inte paus sts1 sts0 strt reserved x r x r x r x r x r x r x r 7654 3210 d6 x r d7 d5 d4 d3 d2 d1 d0 0 w 0 w 0 w 0 w x r x r x r 15 14 13 12 11 10 9 8 st1 0 r/w s10 st0 ct1 ct0 ? d9 d8
mb90470 series 40 (2) block diagram f mp adtg an0 an1 an2 an3 an4 an5 an6 an7 adcr1, adcr2 adcs1, adcs2 av cc avrh av ss d/a converter sequential comparison register input circuit comparator sample & hold circuit data bus decoder data register a/d control register 1 a/d control register 2 trigger start timer start timer (ppg1 output) operating clock prescaler
mb90470 series 41 5. 8/16-bit ppg the 8/16-bit ppg is an 8-bit reload timer module that produces a ppg output in the form of a pulse for timer operation. the hardware configuration includes six 8-bit down counters, twelve 8-bit reload timers, three 16-bit control registers, six external pulse output pins, and six interrupt outputs. the mb90470 provides six 8-bit ppg channels, which can also operate as three 16-bit ppg channels in the combination ppg0 + ppg1, ppg2 + ppg3, ppg4 + ppg5. the following is an overview of the functions of the ppg. ? six-channel independent 8-bit ppg output mode : provides ppg output operation independently on six channels. ? 16-bit ppg output operation mode : provides 16-bit ppg output operation on three channels, using the combination ppg0 + ppg1, ppg2 + ppg3, ppg4 + ppg5. ?8 + 8-bit ppg output operation mode : uses the ppg0 (ppg2/ppg4) output as the ppg1 (ppg3/ppg5) clock input, to enable 8-bit ppg output with any desired period. ? ppg output operation : outputs pulse waves at a specified period and duty ratio. can be also used with an external circuit as a d/a converter.
mb90470 series 42 (1) register list ppgc0 (ppg0/2/4 operating mode control register) ppgc1 (ppg1/3/5 operating mode control register) ppg01/ppg23/ppg45 (ppg0-ppg5 output control register) ppll0 to ppll5 (reload register l) pplh0 to pplh5 (reload register h) 00003a h 00003c h 00003e h read/write default value 00003b h 00003d h 00003f h read/write default value 000040 h 000042 h 000044 h read/write default value 00002e h 000030 h 000032 h 000034 h 000036 h 000038 h read/write default value 00002f h 000031 h 000033 h 000035 h 000037 h 000039 h read/write default value ( ? ) ( x ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( x ) ( ? ) ( x ) ( ? ) ( 1 ) 7654 3210 ? (r/w) ( 0 ) pen0 pe00 pie0 puf0 reserved ?? ( ? ) ( x ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( 1 ) 15 14 13 12 11 10 9 8 ? (r/w) ( 0 ) pen1 pe10 pie1 puf1 md1 md0 reserved (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 pcs1 (r/w) ( 0 ) pcs2 pcs0 pcm2 pcm1 pcm0 reserved reserved (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 d06 (r/w) ( x ) d07 d05 d04 d03 d02 d01 d00 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 d14 (r/w) ( x ) d15 d13 d12 d11 d10 d09 d08
mb90470 series 43 (2) block diagram ? 8 - bit ppg ch 0 / 2 / 4 block diagram s r q prlbh prll prll ppg0/2/4 a/d converter pen0 irq pie0 puf0 ppg 0/2/4 output enable peripheral clock 16 divider peripheral clock 8 divider peripheral clock 4 divider peripheral clock 2 divider peripheral clock ppg 0/2/4 output latch pcnt (down counter) l/h selector count clock selection ch 1/3/5 borrow time base counter output clock 512 divider l/h selection ppgc0 (output mode control) l data bus h data bus
mb90470 series 44 ? 8 - bit ppg ch 1 / 3 / 5 block diagram s r q prlbh prll prll ppg1/3/5 uart0 pen1 irq pie1 puf1 ppg 1/3/5 output enable peripheral clock 16 divider peripheral clock 8 divider peripheral clock 4 divider peripheral clock 2 divider peripheral clock ppg 1/3/5 output latch pcnt (down counter) l/h selector count clock selection time base counter output clock 512 divider l/h selection ppgc1 (output mode control) l data bus h data bus
mb90470 series 45 6. 8/16-bit up-down counter/timer this block is an up-down counter/timer configured with six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and related control circuits. (1) principal functions ? 8-bit count registers for counting in the range 0 to 256. (also operates in 16-bit 1 mode for counting in the range 0 to 65535.) ? count clock selection provides four count modes. ? in timer mode, there is a choice of two internal count clocks. ? in up/down count mode, there is a choice of external pin input signal detection edge. ? in phase differential count mode, to provide counts for encoders for motors, etc., the a phase, b phase, and z phase of the encoder can be input separately for highly precise counts of rotation angle, rotary speed, etc. ? the zin pin provides a choice of two functions. ? compare and reload functions are provided, each available independently or in combination. both can be started together to provide any desired type of up/down count. ? individually controllable interrupts at compare, reload (underflow) and overflow events. ? count direction flag enables detection of immediately preceding count direction. ? interrupt generation at change of count direction. count mode time mode up/down count mode phase differential count mode (2 ) phase differential count mode (8 ) count clock 125 ns (8 mhz : divided by 2) (16 mhz operation) 0.5 m s (2 mhz : divided by 8) detection edge falling edge detection rising edge detection falling/rising edge, both edges detection edge detection disabled zin pin counter clear function gate function compare/reload function compare function (outputs interrupt at compare events) compare function (outputs interrupt and clears count at compare events) reload function (outputs interrupt and reloads at underflow events) compare/reload function (outputs interrupt and clears count at compare events, outputs interrupt and reloads at underflow events) compare/reload disabled
mb90470 series 46 (2) register list ccrh0 (counter control register high ch.0) ccrh1 (counter control register high ch.1) ccrl0/1 (counter control register low ch.0/1) csr0/1 (counter status register ch. 0/1) udcr0/1 (up down count register ch. 0/1) rcr0/1 (reload/compare register ch. 0/1) default value address : 00006d h 00000000 b default value address : 000071 h -0000000 b address address : 00006c h : 000070 h default value 0x00x000 b address address : 000072 h : 000074 h default value 00000000 b default value address : 000069 h 00000000 b default value address : 000068 h 00000000 b default value address : 00006b h 00000000 b default value address : 00006a h 00000000 b rcr0 udcr0 udcr1 rcr1 15 0 ccrl0 csr0 reserved ccrh0 ccrl1 csr1 reserved ccrh1 87 8 bit 8 bit 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w cdcf m16e cfie clks cms1 cms0 ces1 ces0 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w cdcf ? cfie clks cms1 cms0 ces1 ces0 7654 321 0 r/w w r/w r/w w r/w r/w r/w ctut udms ucre rlde udcc cgsc cge1 cge0 7654 321 0 r/w r/w r/w r/w r/w r/w r r cite cstr udie cmpf ovff udff udf1 udf0 15 14 13 12 11 10 9 8 rrrr rrr r d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 rrrr rrr r d06 d07 d05 d04 d03 d02 d01 d00 15 14 13 12 11 10 9 8 wwww www w d16 d17 d15 d14 d13 d12 d11 d10 7654 321 0 wwww www w d06 d07 d05 d04 d03 d02 d01 d00
mb90470 series 47 (3) block diagram cge1 cge0 cgsc carry cms1 cms0 udms ces1 ces0 cite udie udf1 udf0 cdcf cfie ctut ucre rlde udcc cmpf udff ovff clks cstr 8 bit 8 bit ain0 bin0 zin0 data bus rcr0 (reload/compare register 0) edge/level detection reload control counter clear ucdr0 (up/down count register 0) count clock up-down count clock selection prescaler interrupt output
mb90470 series 48 7. dtp/external interrupts the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16l cpu. the dtp receives dma request from external peripherals and passes the requests to the f 2 mc-16l cpu to activate the extended m dma or interrupt processing. (1) register descriptions (2) block diagram interrupt/dtp enable register (enir : enable interrupt request register) interrupt/dtp source register (eirr : external interrupt request register) request level setting register (elvr : external level register) enir default value address : 00000c h 00000000 b eirr default value address : 00000d h 00000000 b (note that both registers relate to different interrupts) default value address : 00000e h 00000000 b default value address : 00000f h 00000000 b 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w er6 er7 er5 er4 er3 er2 er1 er0 7654 321 0 r/w r/w r/w r/w r/w r/w r/w r/w la3 lb3 lb2 la2 lb1 la1 lb0 la0 15 14 13 12 11 10 9 8 r/w r/w r/w r/w r/w r/w r/w r/w la7 lb7 lb6 la6 lb5 la5 lb4 la4 4 interrupt/dtp enable register interrupt/dtp source register interrupt level setting register f 2 mc-16 bus 4 4 8 4 gate source f/f edge detection circuit request input
mb90470 series 49 8. 16-bit input output timer the 16-bit input/output timer is composed of one 16-bit free-run timer module, 6 output compare modules, and 2 input capture modules. these functions can be used to produce output of six independent wave forms based on the 16-bit free-run timer, with input pulse width measurement and external clock period measurement. ? list of registers for all modules ? 16-bit free-run timer ? 16-bit output compare ? 16-bit input capture cpclr 15 0 000066/67 h 000062/63 h 000064/65 h tcdt tccs compare clear register timer data register control status register occp0 to occp5 compare register control status register 15 0 ocs0/2/4 ocs1/3/5 00004a, 4c, 4e, 50, 52, 54 h 00004b, 4d, 4f, 51, 53, 55 h 000056, 58, 5a h 000057, 59, 5b h ipcp0, iccp1 compare register control status register 15 0 ics 00005c, 5e h 00005d, 5f h 000060 h
mb90470 series 50 ? overall block diagram tq tq out0 out1 control logic to blocks interrupt 16-bit free-run timer 16-bit timer compare register 0 compare register 1 clear output compare 0 output compare 1 tq tq out2 out3 compare register 2 compare register 3 output compare 2 output compare 3 in0 in1 capture register 0 capture register 1 edge selection edge selection input capture 0 input capture 1 bus tq tq out4 out5 compare register 4 compare register 5 output compare 4 output compare 5
mb90470 series 51 (1) 16-bit free-run timer the 16-bit free-run timer is composed of a 16-bit up-down counter and control register. the count value from this timer is used as the base timer for the input capture and output compare modules. ? a selection of 8 clock types for counter operation is available. ? counter overflow interrupts can be generated. ? by a mode setting, the counter can be initialized when the timer value matches the compare register value for the output compare module. ? register list compare clear register (cpclr) timer counter data register (tcdt) timer counter control/status register (tccs) default value 000067 h xxxxxxxx b default value 000066 h xxxxxxxx b default value 000063 h 00000000 b default value 000062 h 00000000 b default value 000065 h 0--00000 b default value 000064 h 00000000 b 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) cl14 cl15 cl13 cl12 cl11 cl10 cl09 cl08 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) cl06 cl07 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) t14 t15 t13 t12 t11 t10 t09 t08 7654 321 0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) t06 t07 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ? ecke ? msi2 msi1 msi0 iclr icre 7654 321 0 ( r/w )( r/w )( r/w )( r/w )( r/w )( r/w )( r/w )( r/w ) ivfe ivf stop mode sclr clk2 clk1 clk0
mb90470 series 52 ? block diagram ivf ivfe stop mode sclr clk1 clk0 iclr msi3 to 0 compare circuit icre clk2 f interrupt request frequency divider bus 16-bit free-run timer 16-bit compare clear register count value output t15 to t00 clock interrupt request a/d converter startup
mb90470 series 53 (2) output compare the output compare module consists of a 16-bit compare register, compare output pin unit, and control register. when the value in the compare register in this module matches the value of the 16-bit free-run timer, the pin output level can be inverted and an interrupt generated. ? there are six compare registers that can operate independently. module settings can be used to use the two compare registers to control the output. ? the interrupt can be set by a compare match. ? register list compare register (occp0 to occp5) control register (ocs1/3/5) control register (ocs0/2/4) default value 00004b h 00004d h 00004f h 000051 h 000053 h 000055 h xxxxxxxx b default value 00004a h 00004c h 00004e h 000050 h 000052 h 000054 h xxxxxxxx b default value 000057 h 000059 h 00005b h ---00000 b default value 000056 h 000058 h 00005a h 0000--00 b 15 14 13 12 11 10 9 8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) c14 c15 c13 c12 c11 c10 c09 c08 6543 210 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) c06 c07 c05 c04 c03 c02 c01 c00 15 14 13 12 11 10 9 8 ( ? )( ? )( ? ) (r/w) (r/w) (r/w) (r/w) (r/w) ? ?? cmod ote1 ote0 otd1 otd0 7654 321 0 (r/w) (r/w) (r/w) (r/w) ( ? )( ? ) (r/w) (r/w) icp0 icp1 ice1 ice0 ?? cst1 cst0
mb90470 series 54 ? block diagram icp1 icp0 ice0 ice0 tq tq cmod ote1 ote0 out0 (2) (4) out1 (3) (5) compare 1 (3) (5) interrupt compare 0 (2) (4) interrupt 16-bit timer counter value (t15 to t00) 16-bit timer counter value (t15 to t00) compare control compare register 0 (2) compare control compare register 1 (3) control unit control blocks bus
mb90470 series 55 (3) input capture the input capture module detects the rising edge, falling edge, or both edges of an input signal and saves the value of the 1-bit free-run timer at that moment in a register. this module can also generate an interrupt when an edge is detected. the input capture module is composed of input capture registers and a control register. each of the input captures has a corresponding external input pin. ? selection of three valid edges for external input : rising edge/falling edge/both edges ? an interrupt can be generated when the valid edge is detected. ? register list ? block diagram input capture data registers (ipcp0, ipcp1) control status register (ics0, ics1) default value 00005d h 00005f h xxxxxxxx b default value 00005c h 00005e h xxxxxxxx b default value 000060 h 00000000 b 15 14 13 12 11 10 9 8 ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) cp14 cp15 cp13 cp12 cp11 cp10 cp09 cp08 7654 321 0 ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) ( r ) cp06 cp07 cp05 cp04 cp03 cp02 cp01 cp00 7654 321 0 ( r/w )( r/w )( r/w )( r/w )( r/w )( r/w )( r/w )( r/w ) icp0 icp1 ice1 ice0 eg11 eg10 eg01 eg00 in0 eg11 eg10 eg01 eg00 icp1 icp0 ice1 ice0 in1 capture data register 0 capture data register 1 edge detection edge detection 16-bit timer counter value (t15 to t00) bus interrupt interrupt
mb90470 series 56 9. i 2 c interface the i 2 c interface is a serial i/o port supporting inter ic bus operation, and operates as a master/slave device on the i 2 c bus. the following features are provided. ? master/slave sending and receiving ? arbitration functions ? clock synchronization functions ? slave address/general call address detection functions ? transfer direction detection function ? start condition repeat generator and detection function ? bus error detection function (1) register list ibsr (bus status register) ibcr (bus control register) iccr (clock control register) iadr (address register) idar (data register) bit no. address : 000088 h read/write default value bit no. address : 000089 h read/write default value bit no. address : 00008a h read/write default value bit no. address : 00008b h read/write default value bit no. address : 00008c h read/write default value ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 7654 3210 rsc ( r ) ( 0 ) bb al lrb trx aas gca fbt (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 beie (r/w) ( 0 ) ber scc mss ack gcaa inte int ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 ? ( ? ) ( ? ) ? en cs4 cs3 cs2 cs1 cs0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 a6 ( ? ) ( ? ) ? a5 a4 a3 a2 a1 a0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0
mb90470 series 57 (2) block diagram iccr en iccr ibsr bb rsc lrb last bit repeat start bus busy send/receive trx fbt al ibcr ber beie inte int ibcr scc mss ack gcaa ibsr idar slave address compare iadr aas gca cs4 cs3 cs2 cs1 cs0 2 4 8 16 128 256 32 64 56 7 clock divider 1 clock select 1 clock divider 2 clock select 2 peripheral clock 8 sync first byte irq end interrupt request scl sda i 2 c enable f 2 mc-16 bus shift clock generator shift clock edge change timing start/stop condition detector start/stop condition generator arbitration lost detector error start master ack enable gc-ack enable slave global call
mb90470 series 58 10. 16-bit reload timer the 16-bit reload timer provides a choice of two functions, one is an internal clock countdown synchronized with any of 3 types of internal clock, and the other is an event count mode that counts down at detection of a given edge of a pulse input externally. this timer defines an underflow as a transition of the count value from 0000 h to ffff h . therefore, an underflow will occur at the count value reload register setting count + 1. the count operation includes a choice of reload mode in which the count set value is reloaded at each underflow event, and one-shot mode in which the count stops at an underflow event. an interrupt can be generated when the counter reaches an underflow, and the timer is dtc compatible. (1) register list tmcsr (timer control status registers) timer control status register (high) timer control status register (low) 16-bit timer register/16-bit reload register tmr / tmrlr ( high ) tmr / tmrlr ( low ) 0000cb h read/write default value 0000ca h read/write default value 0000cd h read/write default value 0000cc h read/write default value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? ( ? ) ( ? ) ??? csl1 csl0 mod2 mod1 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 oute (r/w) ( 0 ) mod0 outl reld inte uf cnte trg (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 d14 (r/w) ( x ) d15 d13 d12 d11 d10 d09 d08 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 7654 3210 d06 (r/w) ( x ) d07 d05 d04 d03 d02 d01 d00
mb90470 series 59 (2) block diagram tmrlr tmr en oute reld outl clk clk prescaler uf 3 3 2 function select select signal internal data bus 16-bit reload register 16-bit timer register (down counter) reload signal reload control circuit count clock generator circuit gate input valid clock decision circuit wait signal machine clock f clear output signal generator circuit to a/d converter invert pin (tin0) input control circuit output signal generator circuit pin (tot0) operation control circuit clock selector timer control status register (tmcsr) external clock
mb90470 series 60 11. m m m m pg timer the m pg timer produces a pulse output according to an external input signal. (1) register list (2) block diagram pgcsr (pg control/status register) operating mode control register 00008e h read/write default value (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) 7654 3210 pe1 (r/w) ( 0 ) pen0 pe0 pmt1 pmt0 ??? mt00 mt01 extc output enable mt00 output latch mt00 output latch control circuit
mb90470 series 61 12. pwc (pulse width count) timer the pwc timer is a 16-bit multi-function up-count timer with an input signal pulse width measurement function. the hardware includes a total of three channels, each with one 16-bit up-count timer, one input pulse divider and divider ration control register, one measurement input pin, and one 16-bit control register. the following functions are provided : timer functions : an interrupt can be generated each time a set time interval elapses. a choice of three internal reference clocks is available. pulse width measurement functions : measures the time between designated events on an externally input pulse signal. the reference clock is selected from three internal clock signals. measurement modes : 1) h pulse width ( - to ) /l pulse width ( - to ) 2) rise period ( - to - ) /fall period ( to ) 3) measurement between edges (high or low to low or high) an 8-bit input divider can divide the input pulse into 2 2n divisions (n = 1, 2, 3, 4) and measure the divisions. an interrupt can be generated when measurement is ended. both one-time and continuous measurement are enabled.
mb90470 series 62 (1) register list pwcsr0 to pwcsr2 (pwc control/status registers) pwcr0 to pwcr2 (pwc data buffer registers) divr0 to divr2 (divider control register) 000077 h 00007b h 00007f h read/write default value 000076 h 00007a h 00007e h read/write default value 000079 h 00007d h 000081 h read/write default value 000078 h 00007c h 000080 h read/write default value 000082 h 000084 h 000086 h read/write default value (r/w) (r/w) (r/w) 15 0 87 divr0 to divr2 pwcsr0 to pwcsr2 pwc0 to pwc2 (r/w) ( 0 ) ( r ) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( r ) ( 0 ) ( ? ) ( x ) 15 14 13 12 11 10 9 8 stop (r/w) ( 0 ) strt edir edie ovir ovie err reserved (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 cks0 (r/w) ( 0 ) cks1 pis1 pis0 s/c mod2 mod1 mod0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 d14 (r/w) ( 0 ) d15 d13 d12 d11 d10 d9 d8 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 d6 (r/w) ( 0 ) d7 d5 d4 d3 d2 d1 d0 ( ? ) ( x ) ( ? ) ( x ) ( ? ) ( x ) ( ? ) ( x ) ( ? ) ( x ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 ? ( ? ) ( x ) ????? div1 div0
mb90470 series 63 (2) block diagram err pwcr 16 16 cks1/cks0 15 err cks0/cks1 pis0/pis1 pwcsr divr 2 2 2 2 3 pwc0 pwc1 pwcr read error detector internal clock (machine clock / 4) reload data transfer overflow clock count enable 16-bit up/down timer control circuit clock divider timer clear f 2 mc-16 bus divider clear start edge selection end edge selection measure start edge divider on/off edge detection measure end edge input waveform comparator flag set etc. control bit output measurement end interrupt request 8-bit divider overflow interrupt request divider select
mb90470 series 64 13. watch timer the watch timer is a 15-bit timer using a sub-clock signal. this timer can generate interval interrupts. also, by a register setting, it can be used as a clock source for the watchdog timer. (1) register list (2) block diagram watch timer control register (wtc) 0000aa h default value ( r ) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 sce (r/w) ( 1 ) wdcs wtie wtof wtr wtc2 wtc1 wtc0 wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 10 2 13 2 14 2 15 watch timer control register (wtc) clear watch timer interrupt sub-clock watch counter interval selector interrupt generator circuit to watchdog timer
mb90470 series 65 14. watchdog timer the watchdog timer is a 2-bit counter that uses a count clock signal output by the timer base timer or watch timer and will reset the cpu unless cleared within a specified period of time. (1) register list (2) block diagram watchdog timer control register (wdtc) 0000a8 h default value ( ? ) ( x ) ( r ) ( x ) ( r ) ( x ) ( r ) ( x ) ( w ) ( 1 ) ( w ) ( 1 ) ( w ) ( 1 ) 7654 3210 reserved ( r ) ( x ) ponr wrst erst srst wte wt1 wt0 ponr stbr wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 1 sclk hclk signal / 2 clr clr 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 4 watchdog timer control register (wdtc) watch timer control register (wt0) wdcs bit clock select register (ckscr) scm bit watch mode start time base timer mode start sleep mode start hold status start watchdog timer clr and start counter clear control circuit watchdog reset generator circuit internal reset generator circuit 2-bit counter count clock selector stop mode start clear time base counter hclk : oscillator clock sclk : sub-clock
mb90470 series 66 15. time base timer the time base timer is an 18-bit free-run timer that counts up in synchronization with the internal count clock (base oscillator divided by 2) . it functions as an interval timer with a selection of four types of time intervals. other functions of this timer also include output of a timer signal for the oscillator stabilization wait time and an operating clock signal for the watchdog timer. (1) register list (2) block diagram time base timer control register (tbtc) 0000a9 h ( ? ) ( x ) ( ? ) ( x ) (r/w) ( 0 ) (r/w) ( 0 ) ( w ) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? (r/w) ( 1 ) resv ? tbie tbof tbr tbc1 tbc0 tbie tbof tbr resv ?? tbc1 tbc0 of of of of 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 to ppg timer to watchdog timer time base timer/ counter hclk signal /2 power-on reset stop mode start mode start hold status start ckscr : mcr = 1 ? 0 *1 ckscr : scs = 0 ? 1 *2 clock control unit oscillator stabilization wait to interval selector counter clear control circuit interval timer selector tbof set tbof clear time base timer control register (tbtc) time base timer interrupt signal ? : not used of : overflow hclk : oscillator clock *1 : switches machine clock from main clock or sub-clock to pll clock. *2 : switches machine clock from sub-clock to main clock.
mb90470 series 67 16. clock the clock generator module controls the operation of the internal clocks that produce the operating clock signals for the cpu and peripheral devices. this internal clock signal is called the machine clock, and one period is called a machine cycle. the clock signal from the base oscillator is called the oscillator clock, and the clock signal generated by the internal pll module is called the pll clock. (1) register list clock select register (ckscr) 0000a1 h default value ( r ) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 0 ) ( r/w ) ( 0 ) 15 14 13 12 11 10 9 8 mcm ( r ) ( 1 ) scm ws1 ws0 scs mcs cs1 cs0
mb90470 series 68 (2) block diagram scm hclk sclk mcm ws1 ws0 scs mcs cs1 cs0 stp slp spl rst tmd cg1 cg0 re- served 2 2 x0a x1a rst pin pin pin pin pin x0 x1 mclk standby control circuit low power mode control register (lpmcr) pin high-z control circuit internal reset generator circuit cpu clock control circuit peripheral clock control circuit pin high-impedance control internal reset cpu clock peripheral clock stop, sleep signals stop signal cpu intermittent operation selector standby control circuit intermittent cycle selection interrupt release machine clock clock generator module oscillator stabilization wait release clock selector oscillator stabilization wait period selector divide by 4 pll multiplier circuit sub-clock generator circuit clock select register (ckscr) system clock generator circuit divide by 2 divide by 1024 divide by 2 divide by 4 divide by 4 divide by 4 divide by 2 time base timer to watchdog timer hclk : oscillator clock mclk : main clock sclk : sub-clock
mb90470 series 69 (3) clock signal supply map 4 4 3 x0a x1a x0 hclk mclk uart i/o expansion serial interface 2 ch sclk clock selector pclk x1 f 1234 ppg0, ppg1 ppg2, ppg3 ppg4, ppg5 tin0 tot0 sck0, sin0 sot0 sck1, sck2, sot1, sot2 frck clock generator ratio peripheral function watchdog timer 8/16-bit ppg timer 0 8/16-bit ppg timer 1 8/16-bit ppg timer 2 16-bit reload timer 8/16-bit u/d counter chip select 16-bit output compare 16-bit free-run timer 16-bit input capture 10-bit a/d converter external interrupt watch timer time base timer pll multiplier circuit pin pin pin pin sub-clock generator circuit system clock generator circuit pin pin pin pin pin pin pin pin pin pin pin in0, in1 pin divide by 4 divide by 2 i 2 c interface oscillator stabilization wait control 16-bit pwc 3ch sin1, sin2 pin cs0, cs1, pin cs2, cs3 ain0, ain1 bin0, bin1 zin0, zin1 out0, out1,out2, out3, out4, out5 irq0 to irq7 pin in0, in1 pin pwc1, pwc2, pwc3 pin scl, sda pin an0 to an7, adtg pin pin mt00, mt01 hclk : oscillator clock mclk : main clock sclk : sub-clock pclk : pll clock f : machine clock cpu, m dma m pg
mb90470 series 70 17. low power modes the mb90470 series uses a selection of operating clock signals and clock operation controls to provide the following cpu operating modes. ? clock modes (pll clock mode, main clock mode, sub-clock mode) ? cpu intermittent operation modes (pll clock intermittent operation mode, main clock intermittent operation mode, sub-clock intermittent operation mode) ? standby mode (sleep mode, time base timer mode, stop mode, watch mode) (1) register list low power mode control register (lpmcr) 0000a0 h default value ( w ) ( 0 ) (r/w) ( 0 ) ( w ) ( 1 ) (r/w) ( 1 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 7654 3210 slp ( w ) ( 0 ) stp spl rst tmd cg1 cg0 reserved
mb90470 series 71 (2) block diagram scm hclk sclk mcm ws1 ws0 scs mcs cs1 cs0 stp slp spl rst tmd cg1 cg0 2 2 x0a x1a rst pin pin pin pin pin x0 x1 mclk standby control circuit low power mode control register (lpmcr) pin high-z control circuit internal reset generator circuit cpu clock control circuit peripheral clock control circuit pin high-impedance control internal reset cpu clock peripheral clock stop, sleep signals stop signal cpu intermittent operation selector standby control circuit intermittent cycle selection interrupt release machine clock clock generator module oscillator stabilization wait release clock selector oscillator stabilization wait period selector divide by 4 pll multiplier circuit sub-clock generator circuit clock select register (ckscr) system clock generator circuit divide by 2 divide 1024 divide by 2 divide by 4 divide by 4 divide by 4 divide by 2 time base timer to watchdog timer re- served hclk : oscillator clock mclk : main clock sclk : sub-clock
mb90470 series 72 (3) status transition chart stp = 1 interrupt stp = 1 stp = 1 tmd = 0 tmd = 0 tmd = 0 slp = 1 interrupt slp = 1 slp = 1 mcs = 0 mcs = 1 scs = 0 scs = 0 scs = 1 scs = 1 external reset, watchdog timer reset, software reset power on power-on reset oscillator stabilization wait end main clock mode interrupt oscillator stabilization wait end main sleep mode main stop mode main clock oscillator stabilization wait time base timer mode interrupt interrupt pll clock mode interrupt oscillator stabilization wait end pll sleep mode pll stop mode main clock oscillator stabilization wait time base timer mode interrupt interrupt sub-clock mode interrupt oscillator stabilization wait end sub-sleep mode sub-stop mode sub-clock oscillator stabilization wait watch mode reset
mb90470 series 73 18. overview of the chip select function this module issues chip select signals in order to facilitate connection to external memory. there are four chip select output pins, with hardware areas set using a register for each output, so that the select signal is output from the related pin whenever access to an external address is detected. ? features of the chip select function the chip select function has two 8-bit registers for settings for each of the four output pins. one register (carx) is used to specify the upper 8 bits of the address for match detection, thereby providing memory area detection in 64 kb units. the other register (cmrx) can be set to detect areas larger than 64 kb by masking bits in the match detection value. note that the cs output is set to high impedance during a bus hold condition. (1) register list chip select area mask register (cmrx) chip select area register (carx) chip select control register (cscr) chip selector active level register (calr) 0000c0 h 0000c2 h 0000c4 h 0000c6 h read/write default value 0000c1 h 0000c3 h 0000c5 h 0000c7 h read/write default value 0000c8 h read/write default value 0000c9 h default value cmr1 cmr0 car0 (r/w) (r/w) car1 15 0 cmr3 cmr2 car2 (r/w) (r/w) car3 cscr (r/w) calr (r/w) 87 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1) (r/w) ( 1 ) 7654 3210 m6 (r/w) ( 0 ) m7 m5 m4 m3 m2 m1 m0 (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) 15 14 13 12 11 10 9 8 a6 (r/w) ( 1 ) a7 a5 a4 a3 a2 a1 a0 ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( * ) 7654 3210 ? ( ? ) ( ? ) ??? opl3 opl2 opl1 opl0 ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? ( ? ) ( ? ) ??? actl3 actl2 actl1 actl0
mb90470 series 74 (2) block diagram a23 to a16 cmrx carx fmc-16 bus chip select output pin
mb90470 series 75 19. rom mirror function select module the rom mirror function select module provides a register selection that allows the ff bank in rom to be viewed in the 00 bank. (1) register list (2) block diagram note : do not access this register during operations to address 004000 h to 00ffff h . w : write only - : not used bit default value romm address : 00006f h - - - - - - - 1 b w 15 14 13 12 11 10 9 8 ? ? ? ???? mi rom address area rom mirror function select f 2 mc-16lx ff bank 00 bank
mb90470 series 76 20. interrupt controller the interrupt control registers are located in the interrupt controller. an interrupt control register is provided for each i/o with an interrupt function. the registers have the following functions. ? set the interrupt level of the corresponding peripheral. (1) register list note : do not access these registers using read-modify-write instructions as this can cause misoperation. (2) block diagram -- -- il2 il1 il0 15 14 13 12 11 10 9 8 icr00 icr02 icr04 icr06 icr08 icr14 : 0000b0 h : 0000b2 h : 0000b4 h : 0000b6 h : 0000b8 h : 0000be h icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 -- -- re- served il2 il1 il0 15 14 13 12 11 10 9 8 : 0000b1 h : 0000b3 h : 0000b5 h : 0000b7 h : 0000b9 h : 0000bb h : 0000bd h : 0000bf h bit (w) (w) (w) (w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (1) (1) (1) (w) (w) (w) (w) (r/w) (r/w) (r/w) (r/w) (0) (0) (0) (0) (0) (1) (1) (1) bit re- served interrupt control register address: read/write ? initial value ? icr01, 03, 05, 07, 09, 11, 13, 15 address: read/write ? initial value ? icr00, 02, 04, 26, 08, 10, 12, 14 re- il2 il1 il0 32 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 served determine priority of interrupt interrupt request (peripheral resource) (cpu) interrupt level f 2 mc-16lx bus
mb90470 series 77 21. m m m m dma m dma is the simplified dma which has the equivalent function to ei 2 os function m dma has dma transfer channel which consists of 16 channels and has the following functions. ? automatic data transfer between peripheral resources (i/o) and memory. ? cpu program executing stops dring dma operation. ? selectable for address transfer increase/decrease . ? dma transfer control is done at dma enable register, dma stop status register, dma status register and descriptor. ? stop request stops dma transfer from resources. ? after dma transfer, flag is set to bit corresponding to dma status register transfer stop channel and stop interrupt is output to interrupt controller. (1) register list dma enable register dma enable register dma stop status register dma status register dma status register bit initial value derh : 0000ad h 0 0 0 0 0 0 0 0 b bit initial value derl : 0000ac h 0 0 0 0 0 0 0 0 b bit initial value dssr : 0000a4 h 0 0 0 0 0 0 0 0 b bit initial value dsrh : 00009d h 0 0 0 0 0 0 0 0 b bit initial value dsrl : 00009c h 0 0 0 0 0 0 0 0 b (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 en14 (r/w) en15 en13 en12 en11 en10 en9 en8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 7654 3210 en6 (r/w) en7 en5 en4 en3 en2 en1 en0 7654 3210 stp6 stp7 stp5 stp4 stp3 stp2 stp1 stp0 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) 15 14 13 12 11 10 9 8 de14 de15 de13 de12 de11 de10 de9 de8 (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) (r/w) ( r/w ) ( r/w ) ( r/w ) (r/w) (r/w) (r/w) (r/w) 7654 3210 de6 ( r/w ) de7 de5 de4 de3 de2 de1 de0
mb90470 series 78 (2) block diagram cpu by bap by ioa by dct f 2 mc-16lx bus memory area i/o register transfer buffer dma descriptor i/o register peripheral functions (i/o) not transfer stop der read dma transfer request dma controller interrupt controller at transfer stop ioa : address pointer bap : buffer address pointer der : dma enable register (enx selection is done.) dtc : data counter
mb90470 series 79 22. external bus pin control circuit the external bus pin control circuit controls the external bus pins used to expand the cpu address/data bus connections to external circuits. (1) register list (2) block diagram ? auto ready function select register (arsr) ? external address output control register (hacr) ? bus control signal select register (epcr) initial value address : 0000a5 h 0011- - 00 b initial value address : 0000a6 h 00000000 b initial value address : 0000a7 h 1000 * 10 - b w - * : write only : not used : may be either 1 or 0 www ?? ww bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 icr0 w icr1 hmr1 hmr0 ?? lmr1 lmr0 w w w w www bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e22 w e23 e21 e20 e19 e18 e17 e16 wwww ww ? bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 rye w cke hde icbs hmbs wre lmbs ? p3 p2 p1 p0 p0 p5 rb p4 p5 access control access control address control data control p0 direction p0 data
mb90470 series 80 23. address match detection function when the address is equal to a value set in the address detection register, the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code (01h). as a result, when the cpu executes a set instruction, the int9 instruction is executed. processing by the int#9 interrupt routine allows the program patching function to be implemented. two address detection registers are supported. an interrupt enable bit is prepared for each register. if the value set in the address detection register matches an address and if the interrupt enable bit is set at 1, the instruction code loaded into the cpu is replaced forcibly with the int9 instruction code. (1) register configuration ? program address detection register 0 to 2 (padr0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b r/w :readable and writable x :undefined resv:reserved bit address padr0 (low order address): 001ff0 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr0 (middle order address): 001ff1 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr0 (high order address): 001ff2 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (low order address): 001ff3 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (middle order address): 001ff4 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value xxxxxxxx b address padr1 (high order address): 001ff5 h r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 00000000 b address 00009e h r/w r/w r/w r/w r/w r/w r/w r/w ? program address detection register 3 to 5 (padr1) ? program address detection control status register (pacsr) resv resv resv resv ad1e resv ad0e resv
mb90470 series 81 (2) block diagram internal data bus address latch enable bit f 2 mc-16lx cpu core address detection register compare int9 instruction
mb90470 series 82 n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1: av cc and avrh must not exceed v cc 3. also, avrh must not exceed av cc ,too. *2: v i , and v o must not exceed v cc (including v cc 3, v cc 5) plus 0.3 v. *3: maximum output current is defined as the peak value at one corresponding pin. *4: average output current is defined as the average current flowing through one corresponding pin in an interval of 100 ms. *5: average total output current is defined as the total average current flowing through all corresponding pins in an interval of 100 ms. *6: applicable to pins: general purpose cmos input port (p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 to pa3) use within recommended operating conditions. use at dc voltage (current) the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. (continued) parameter symbol rating unit remarks min max supply voltage v cc 3v ss - 0.3 v ss + 4.0 v v cc 5v ss - 0.3 v ss + 7.0 v av cc v ss - 0.3 v ss + 4.0 v *1 avrh v ss - 0.3 v ss + 4.0 v input voltage v i v ss - 0.3 v ss + 4.0 v *2 v ss - 0.3 v ss + 7.0 v *2 output voltage v o v ss - 0.3 v ss + 4.0 v *2 v ss - 0.3 v ss + 7.0 v *2 maximum clamp current i clamp - 2.0 + 2.0 ma *6 total maximum clump current s | i clamp | ? 20 ma *6 l level maximum output current i ol ? 10 ma *3 l level average output current i olav ? 3ma*4 l level maximum total output current s i ol ? 60 ma l level average total output current s i olav ? 30 ma *5 h level maximum output current i oh ? - 10 ma *3 h level average output current i ohav ? - 3ma*4 h level maximum total output current s i oh ? - 60 ma h level average total output current s i ohav ?- 30 ma *5 power consumption p d ? 410 mw operating temperature t a - 40 + 85 c storage temperature tstg - 55 + 150 c
mb90470 series 83 (continued) the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the + b input pin open. sample recommended circuits: warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90470 series 84 2. recommended operating conditions (v ss = av ss = 0.0 v) * : pay attention to operating frequency. note : when using i 2 c functions, the voltage should be at least 2.4 v. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max supply voltage v cc 3* 1.8 3.6 v mask version 2.4 3.6 v low voltage flash version 3.0 3.6 v high speed flash version v cc 5* 1.8 5.5 v mask version 2.4 5.5 v low voltage flash version 3.0 5.5 v high speed flash version v cc 3 1.8 3.6 v hold stop status v cc 5 1.8 5.5 v hold stop status (mask version) 1.8 5.5 v hold stop status (flash version) h level input voltage v ih 0.7 v cc v cc + 0.3 v all pins other than v his , v ihm pins v ihs 0.8 v cc v cc + 0.3 v hysteresis input pins v ihm v cc - 0.3 v cc + 0.3 v md pin input l level input voltage v il v ss - 0.3 0.3 v cc v all pins other than v ils , v ilm pins v ils v ss - 0.3 0.2 v cc v hysteresis input pins v ilm v ss - 0.3 v ss + 0.3 v md pin input operating temperature t a - 40 + 85 c
mb90470 series 85 3. dc characteristics (mask version : v cc = 1.8 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * (low voltage flash version : v cc = 2.4 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * (high speed flash version : v cc = 3.0 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * * : pay attention to operating frequency. (continued) parameter sym- bol pin name conditions value unit remarks min typ max h level output voltage v oh all pins except p76-p77 v cc = 2.7 v i oh = - 1.6 ma v cc 3 - 0.3 ?? v v cc = 4.5 v i oh = - 4.0 ma v cc 5 - 0.5 ?? v using 5 v system power supply l level output voltage v ol all output pins v cc = 2.7 v i ol = 2.0 ma ?? 0.4 v v cc = 4.5 v i ol = 4.0 ma ?? 0.4 v using 5 v system power supply input leak current i il all pins except p76, p77 v cc = 3.3 v v ss < v i < v cc - 10 ? + 10 m a pull-up resistance r pull ? v cc = 3.0 v, at t a = + 25 c 20 65 200 k w open drain output current i leak p40 to p47, p70 to p77 ?? 0.1 10 m a supply current i cc ? at v cc = 3.3 v, at normal internal 20 mhz operation ? 60 80 ma mask version ? 65 85 ma mask version (a/d operation) ? 51 66 ma flash version ? 56 71.5 ma flash version (a/d operation) at v cc = 3.3 v, flash write/erase at internal 20 mhz ? 57 71.5 ma flash version i ccs ? v cc = 3.3 v, sleep mode at 20 mhz ? 18 33 ma i ccl ? at v cc = 3.3 v, sub operation, external 32 khz, internal 8 khz operation (t a = + 25 c) ? 16 140 m a
mb90470 series 86 (continued) (mask version : v cc = 1.8 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * (low voltage flash version : v cc = 2.4 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * (high speed flash version : v cc = 3.0 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * * : pay attention to operating frequency. notes : pins p40-p47 and p70-p75 are n-ch open drain pins with controls, and normally used at cmos level. p76 and p77 are n-ch open drain pins. v cc = v cc 3 = v cc 5. when using two power supplies, the 5 v system pins are p20 to p27, p30 to p37, p40 to p47 and p70 to p77. all other pins are 3 v input/output pins. parameter sym- bol pin name conditions value unit remarks min typ max supply current i cct ? at v cc = 3.3 v, watch operation, external 32 khz, internal 8 khz operation (t a = + 25 c) ? 10 40 m a mask version ? 15 40 m aflash version i cch ? t a = + 25 c, stop mode, at v cc = 3.3 v ? 0.1 20 m a mask version ? 0.2 40 m aflash version input capacitance c in all pins except av cc , av ss , v cc , v ss ?? 515pf
mb90470 series 87 4. ac characteristics (1) clock timing ratings (v ss = 0.0 v, t a = - 40 c to + 85 c) *1 : v cc = v cc 3 = v cc 5 *2 : observe the operating voltage with care. parameter sym- bol pin name conditions value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 20 mhz for crystal oscillation* 2 3 ? 40 for external clock f cl x0a, x1a ?? 32.768 ? khz clock cycle time t c x0, x1 ? 25 ? 333 ns *2 t cl x0a, x1a ?? 30.5 ?m s input clock pulse width p wh p wl x0 ? 5 ?? ns *1 p wlh p wll x0a ?? 15.2 ?m s*1 input clock rise, fall time t cr t cf x0 ??? 5ns using external clock internal operating clock frequency f cp ?? 1.5 ? 20 mhz *2 ?? 1.5 ? 16 mhz mb90474 only f cpl ?? ? 8.192 ? khz 3 ? 20 mhz mb90f474h 3 ? 12 mhz mb90f474l internal operating clock cycle time t cp ?? 50.0 ? 666 ns *2 ?? 62.5 ? 666 ns mb90474 only t cpl ??? 122.1 ?m s
mb90470 series 88 ? x0 , x1 clock timing x0 t c t cf t cr 0.8 v cc 0.2 v cc p wh p wl ? x0a , x1a clock timing x0a t cl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll
mb90470 series 89 ac characteristics are determined using the following measurement reference voltage values. 3.6 1.8 2.4 2.5 3.0 3.13 3 1.5 5 12 16 10 internal clock f cp (mhz) 20 high speed flash model operating range pll warranted operating range supply voltage v cc (v) low voltage flash model operating range normal operating range 16 12 20 8 9 4 34 8 10 16 24 20 32 40 base oscillator clock f c (mhz) internal clock f cp (mhz) internal operating clock frequency vs. supply voltage base oscillator frequency vs. internal operating clock frequency ? pll warranted operating range note : use it at f = 16 mhz for mb90474. when using the high speed flash model at f = 20 mhz, use supply voltages of 3.13 v to 3.6 v. for a/d operating frequencies, see the electrical characteristics of the a/d converter module. maximum assured operation frequency (f cp ) of m dma is 16 mhz. note : use pll circuit when using internal clock at 16 mhz or more. it is recommended to use base oscillator clock of up to 20 mhz. 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pins pins other than hysteresis input/md input pins ? output signal waveform output pins
mb90470 series 90 (2) clock output timing (v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 parameter sym- bol pin name conditions value unit remarks min max cycle time t cyc clk ? t cp ? ns clk -? to clk t chcl clk v cc = 3.0 v to 3.6 v t cp / 2 - 15 t cp / 2 + 15 ns at f cp = 20 mhz v cc = 2.7 v to 3.3 v t cp / 2 - 20 t cp / 2 + 20 ns at f cp = 16 mhz v cc = 2.7 v to 3.3 v t cp / 2 - 64 t cp / 2 + 64 ns at f cp = 5 mhz clk t cyc 2.4 v 2.4 v 0.8 v t chcl
mb90470 series 91 (3) reset input ratings (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * : oscillator oscillation time is the time to reach 90 % amplitude. for a crystal oscillator, this is a few to several dozen ms; for a far/ceramic oscillator, this is several hundred m s to a few ms, and for an external clock this is 0 ms. note: t cp : see (1) clock timing ratings. parameter symbol pin name conditions value unit remarks min max reset input time t rstl rst ? 16 t cp ? ns in normal operation oscillator oscillation time* + 16 t cp ? ms in stop mode rst x0 16 tcp t rstl 0.2 vcc 0.2 vcc internal operation clock internal reset 90 % of amplitude oscillator oscillation time oscillator stabilization wait time execution of the instruction in stop mode c l pin ? measurement conditions for ac ratings c l : load capacitance applied to pin during testing clk, ale, c l = 30 pf ad15 to ad00 (address, data bus) , rd , wr , a23 to a00/d15 to d00 : c l = 80 pf
mb90470 series 92 (4) power on ratings (power-on reset) (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) * : power supply rise time requires v cc < 0.2 v. notes : v cc = v cc 3 = v cc 5 the above ratings are values for power-on reset. a power-on reset should be applied by restarting the power supply inside the device. parameter sym- bol pin name condi- tions value unit remarks min max power rise time t r v cc ? ? 30 ms * power cutoff time t off v cc 1 ? ms for continuous operation v cc v cc v ss t r t off 2.7 v hold ram data 0.2 v 0.2 v 0.2 v main supply voltage sub supply voltage a rise slope of 50 mv or less is recommended extreme variations in supply voltage may activate a power-on reset. as the illustration shows below , when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended.
mb90470 series 93 (5) bus read timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 parameter sym- bol pin name condi- tions value unit remarks min max ale pulse width t lhll ale ? t cp / 2 - 15 ? ns at f cp = 20 mhz t cp / 2 - 20 ? ns at f cp = 16 mhz t cp / 2 - 35 ? ns at f cp = 8 mhz valid address ? ale time t avll address pins, ale ? t cp / 2 - 20 ? ns t cp / 2 - 40 ? ns at f cp = 8 mhz ale ? address valid time t llax ale, address pins ? t cp / 2 - 15 ? ns valid address ? rd time t avrl rd , address ? t cp - 20 ? ns valid address ? valid data input t avdv address/data ? ? 5 t cp / 2 - 60 ns ? 5 t cp / 2 - 80 ns at f cp = 8 mhz rd pulse width t rlrh rd ? 3 t cp / 2 - 25 ? ns at f cp = 20 mhz 3 t cp / 2 - 20 ? ns at f cp = 16 mhz rd ? valid data input t rldv rd , data ? ? 3 t cp / 2 - 60 ns ? 3 t cp / 2 - 80 ns at f cp = 8 mhz rd - ? data hold time t rhdx rd , data ? 0 ? ns rd - ? ale - time t rhlh rd , ale ? t cp / 2 - 15 ? ns rd - ? address valid time t rhax address, rd ? t cp / 2 - 10 ? ns valid address ? clk - time t avch address, clk ? t cp / 2 - 20 ? ns rd ? clk - time t rlch rd , clk ? t cp / 2 - 20 ? ns ale ? rd time t llrl rd , ale ? t cp / 2 - 15 ? ns
mb90470 series 94 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc clk ale rd a23 to a16 ad15 to ad00 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc a23 to a00 d15 to d00 t rldv t rhax t rhdx t avdv 0.8 v 2.4 v address read data read data multiplex mode non-multiplex mode
mb90470 series 95 (6) bus write timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 parameter sym- bol pin name condi- tions value unit remarks min max valid address ? wr time t avwl address pins, wr ? t cp - 20 ? ns wr pulse width t wlwh wrl , wrh ? 3 t cp / 2 - 25 ? ns at f cp = 20 mhz ? 3 t cp / 2 - 20 ? ns at f cp = 16 mhz valid data output ? wr - time t dvwh data pins, wr ? 3 t cp / 2 - 20 ? ns wr - ? data hold time t whdx wr , data pins ? 15 ? ns at f cp = 20 mhz ? 20 ? ns at f cp = 16 mhz ? 30 ? ns at f cp = 8 mhz wr - ? address valid time t whax wr , address pins ? t cp / 2 - 10 ? ns wr - ? ale - time t whlh wr , ale ? t cp / 2 - 15 ? ns wr ? clk - time t wlch wr , clk ? t cp / 2 - 20 ? ns
mb90470 series 96 wr (wrl, wrh) 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale a23 to a16 ad15 to ad00 t whlh t avwl t dvwh t dvwh t wlwh t whax t whdx t wlch 0.8 v 2.4 v 0.8 v 2.4 v a23 to a00 d15 to d00 t whax t whdx 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v address write data write data multiplex mode non-multiplex mode
mb90470 series 97 (7) ready input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : if the rdy setup time is not sufficient, use the auto ready function. v cc = v cc 3 = v cc 5 if input from the rdy pin, note that the ac ratings must be satisfied so that the chip will not drive recklessly. parameter symbol pin name condi- tions value unit remarks min max rdy setup time t ryhs rdy ? 45 ? ns ? 70 ? ns f cp = 8 mhz rdy hold time t ryhh ? 0 ? ns t ryhh 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc clk ale rdy wait not applied rdy wait applied (1 cycle) rd/wr t ryhs t ryhs
mb90470 series 98 (8) hold timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 if the hrq pin is read, at least one cycle is required before the hak pin changes. parameter symbol pin name condi- tions value unit remarks min max pin floating ? hak time t xhal hak ? 30 t cp ns hak ? valid data time t hahv hak t cp 2 t cp ns hak all pins t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v high-z
mb90470 series 99 (9) uart timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : these ac characteristics are for operation in clk synchronous mode. c l is the load capacitance applied to pins during testing. t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 parameter sym- bol pin name conditions value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode output pin c l = 80 pf + 1 ttl 8 t cp ? ns sck ? sot delay time t slov ? - 80 + 80 ns - 120 + 120 ns f cp = 8 mhz valid sin ? sck - t ivsh ? 100 ? ns 200 ? ns f cp = 8 mhz sck - ? valid sin hold time t shix ? t cp ? ns serial clock h pulse width t shsl ? external shift clock mode output pin c l = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh ? 4 t cp ? ns sck ? sot delay time t slov ? ? 150 ns ? 200 ns f cp = 8 mhz valid sin ? sck - t ivsh ? 60 ? ns 120 ? ns f cp = 8 mhz sck - ? valid sin hold time t shix ? 60 ? ns 120 ? ns f cp = 8 mhz
mb90470 series 100 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90470 series 101 (10) i/o expanded serial interface timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : these ac ratings are for operation in clk synchronous mode. c l is the load capacitance applied to pins during testing. t cp : see (1) clock timing ratings. values shown are target values. v cc = v cc 3 = v cc 5 parameter sym- bol pin name conditions value unit remarks min max serial clock cycle time t scyc ? internal shift clock mode output pin c l = 80 pf + 1 ttl 8 t cp ? ns sck ? sot delay time t slov ? - 80 + 80 ns - 120 + 160 ns f cp = 8 mhz valid sin ? sck - t ivsh ? 100 ? ns 200 ? ns f cp = 8 mhz sck - ? valid sin hold time t shix ? t cp ? ns serial clock h pulse width t shsl ? external shift clock mode output pin c l = 80 pf + 1 ttl 4 t cp ? ns serial clock l pulse width t slsh ? 4 t cp ? ns sck ? sot delay time t slov ? ? 150 ns ? 200 ns f cp = 8 mhz valid sin ? sck - t ivsh ? 60 ? ns 120 ? ns f cp = 8 mhz sck - ? valid sin hold time t shix ? 60 ? ns 120 ? ns f cp = 8 mhz
mb90470 series 102 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90470 series 103 (11) i 2 c timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) note : v cc = v cc 3 = v cc 5 parameter sym- bol pin name condi- tions value unit remarks min max scl clock frequency f scl ? ? 0100khz bus free time between stop and start t bus ? 4.7 ?m s hold time (resend) start t hdsta ? 4.0 ?m s first clock pulse is generated after this interval. scl clock l status hold time t low ? 4.7 ?m s scl clock h status hold time t high ? 4.0 ?m s resend start condition setup time t susta ? 4.7 ?m s data hold time t hddat ? 0 ?m s data setup time t sudat ? 40 ? ns sda and scl signal rise time t r ?? 1000 ns sda and scl signal fall time t f ?? 300 ns stop condition setup time t susto ? 4.0 ?m s sda scl t bus t hdsta t hddat t sudat t susta t susto t low t high t hdsta 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t r t f f scl
mb90470 series 104 (12) timer input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 (13) timer output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) note : v cc = vcc3 = v cc 5 parameter symbol pin name condi- tions value unit remarks min max input pulse width t tiwh t tiwl tin0, in0, in1, pwc0 to pwc3 ? 4 t cp ? ns parameter sym- bol pin name condi- tions value unit remarks min max clk - ? tout change time ppg0 to ppg5 change time out0 to out5 change time t to tot0, ppg0 to ppg5, out0 to out5 80 pf load 30 ? ns 0.8 v cc tin0, pwc0 to pwc3, in0, in1 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.7 v cc clk t out, ppg0 to ppg5, out0 to out5 0.3 v cc 0.7 v cc t to
mb90470 series 105 (14) trigger input timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 (15) up/down counter timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 parameter symbol pin name condi- tions value unit remarks min max input pulse width t trgh t trgl adtg, irq0 to irq7 ? 5 t cp ? ns in normal operation 1 ?m s stop mode parameter sym- bol pin name condi- tions value unit remarks min max ain input h pulse width t ahl ain0, ain1, bin0, bin1 80 pf load 8 t cp ? ns ain input l pulse width t all 8 t cp ? ns bin input h pulse width t bhl 8 t cp ? ns bin input l pulse width t bll 8 t cp ? ns ain - ? bin - time t aubu 4 t cp ? ns bin - ? ain time t buad 4 t cp ? ns ain ? bin - time t adbd 4 t cp ? ns bin ? ain - time t bdau 4 t cp ? ns bin - ? ain - time t buau 4 t cp ? ns ain - ? bin time t aubd 4 t cp ? ns bin ? ain - time t bdad 4 t cp ? ns ain ? bin - time t adbu 4 t cp ? ns zin input h pulse width t zhl zin0, zin1 4 t cp ? ns zin input l pulse width t zll 4 t cp ? ns 0.8 v cc irq0 to irq7, adtg 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
mb90470 series 106 0.2 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc t all t bll t bhl t ahl t aubu t buad t adbd t bdau ain bin 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc t buau t aubd t zhl t zll t bdad t adbu bin ain zin
mb90470 series 107 (16) chip select output timing (v cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = - 40 c to + 85 c) notes : t cp : see (1) clock timing ratings. v cc = v cc 3 = v cc 5 note : the chip select output signal changes at the same time due to the structure of the internal bus, leading to the possibility of a bus fight. ac warranty does not apply between ale output signals and chip select output signals. parameter sym- bol pin name condi- tions value unit remarks min max chip select output valid time ? rd t svrl cs0 to cs3, rd ? t cp / 2 - 10 ? ns chip select output valid time ? wr t svwl cs0 to cs3, wrh , wrl ? t cp / 2 - 10 ? ns rd - ? chip select output valid time t rhsv rd , cs0 to cs3 ? t cp / 2 - 20 ? ns wr - ? chip select output valid time t whsv wrh , wrl , cs0 to cs3 ? t cp / 2 - 20 ? ns t svrl t svwl t whsv read data write data un- defined t rhsv 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v rd a23 to a16, cs0 to cs3 d15 to d00 wrh, wrl d15 to d00
mb90470 series 108 5. a/d converter electrical characteristics (v cc = av cc = 1.8 v to 3.6 v, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) *1 : at machine clock frequency 16 mhz. *2 : current with a/d converter not operating, and cpu in stop mode (v cc = av cc = avrh = 3.0 v) parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb at v cc = av cc = 2.2 v to 3.6 v 4.0 lsb at v cc = av cc = 1.8 v to 2.2 v linear error ?? ? ? 2.5 lsb at v cc = av cc = 2.2 v to 3.6 v 3.0 lsb at v cc = av cc = 1.8 v to 2.2 v differential linear error ?? ? ? 1.9 lsb at v cc = av cc = 2.2 v to 3.6 v 2.4 lsb at v cc = av cc = 1.8 v to 2.2 v zero transition voltage v ot an0 to an7 av ss - 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv at v cc = av cc = 2.2 v to 3.6 v av ss - 2.0 lsb av ss + 0.5 lsb av ss + 3.0 lsb mv at v cc = av cc = 1.8 v to 2.2 v full scale transition voltage v fst an0 to an7 avrh - 3.5 lsb avrh - 1.5 lsb avrh + 0.5 lsb mv at v cc = av cc = 2.2 v to 3.6 v avrh - 4.0 lsb avrh - 1.5 lsb avrh + 1.0 lsb mv at v cc = av cc = 1.8 v to 2.2 v conversion time ?? 5.8125* 1 ??m s at avrh 3 2.7 v analog port input current i ain an0 to an7 ? 0.1 10 m a analog input voltage v ain an0 to an7 av ss ? avrh v reference voltage ? avrh av ss + 2.2 ? av cc v at v cc = av cc = 2.2 v to 3.6 v av ss + 1.8 ? av cc v at v cc = av cc = 1.8 v to 2.2 v supply current i a av cc ? 1.2 4.4 ma i ah av cc ?? 5* 2 m a reference voltage supply current i r avrh ? 95 170 m a i rh avrh ?? 5* 2 m a inter-channel variation ? an0 to an7 ?? 4lsb
mb90470 series 109 notes : v cc = v cc 3 = v cc 5 the relative error increases as |avrh - av ss | is reduced. observe the following conditions in applying output impedance on the external circuits of the analog input. output impedance on the external circuit is recommended to be 6 k w or less. if external capacitance is used, it is recommended that this be several thousand times the level of internal capacitors in view of the effects of voltage division between the external capacitor and the interior of the chip. if the output impedance of the external circuits is too high, the analog voltage sampling time may be insufficient. (sampling time = 3.00 m s at machine clock frequency 20 mhz) . < reference data > ? analog input circuit ? a/d operating frequency restrictions supply voltage a/d conversion time [ m m m m s] machine clock frequency 3.6 v 3 av cc 3 3.0 v 4.650 20 mhz 3.6 v 3 av cc 3 2.7 v 5.813 16 mhz 2.7 v > av cc 3 2.6 v 6.643 14 mhz 2.6 v > av cc 3 2.5 v 7.750 12 mhz 2.5 v > av cc 3 2.4 v 8.455 11 mhz 2.4 v > av cc 3 2.3 v 9.300 10 mhz 2.3 v > av cc 3 2.2 v 11.63 8 mhz 2.2 v > av cc 3 2.1 v 15.50 6 mhz 2.1 v > av cc 3 2.0 v 23.25 4 mhz 2.0 v > av cc 3 1.9 v 46.50 2 mhz 1.9 v > av cc 3 1.8 v 93.00 1 mhz r on1 r on2 r on3 r on4 c 0 c 1 analog input comparator sample and hold circuit note : values shown here are intended as guidelines. ? model analog input circuit r on1 : approx. 5 k w r on2 : approx. 617 w r on3 : approx. 617 w r on4 : approx. 473 w c 0 : approx. 35 pf c 1 : approx. 2 pf
mb90470 series 110 ? use of the x0 / x1 , x0a / x1a pins ? sample use of external clock input 6. flash memory program/erase characteristics parameter conditions value unit remarks min typ max sector erase time t a = + 25 c v cc = 3.3 v ? 1 15 s excludes 00 h programming prior erasure chip erase time ? 7 ? s excludes 00 h programming prior erasure word (16-bit) programming time ? 16 3600 m s excludes system-level overhead erase/program cycle ? 1000 ?? cycle data hold time ? 100000 ?? h x1 c2 c3 c4 c1 x0 x0a x1a pull-up resistance 1 pull-up resistance 2 damping resistance 1 damping resistance 2 use with a crystal oscillator in normal use (v cc = 2 v or higher) pull-up resistance 1, 2 damping resistance 1, 2 c1 to c4 for all pins, consult regarding manufacturer of oscillator. (sample operation using v cc = 2 v, f = 5 mhz or less) pull-up resistance 1 = 5.1 k w pull-up resistance 2 = 510 k w damping resistance 1 = 0 w damping resistance 2 = 39 k w c1 = c2 = 22 pf c3 = c4 = 30 pf x0 x1 open mb90470 series
mb90470 series 111 n sample characteristics (1) h level output voltage (2) l level output voltage (3) h level input voltage/ l level input voltage (cmos input) (4) h level input voltage/ l level input voltage (hysteresis input) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 - 1 - 2 - 3 - 4 - 5 v cc = 2.7 v v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v v cc = 3.9 v t a = + 25 c v oh (v) i oh (ma) (v cc - v oh ) - i oh v ol (v) i ol (ma) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 12345 t a = + 25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.3 v v cc = 3.6 v v cc = 3.9 v v ol - i ol v in (v) v cc (v) t a = + 25 c v il v ih 2.5 2.0 1.5 1.0 0.5 0.0 2.7 3.0 3.3 3.6 3.9 v in - v cc v in (v) t a = + 25 c v ih v il 2.5 2.0 1.5 1.0 0.5 0.0 2.7 3.0 3.3 3.6 3.9 v cc (v) v in - v cc
mb90470 series 112 (5) supply current (f cp = = = = internal stroke frequency) ? mask versions 90 80 70 60 50 40 30 20 10 0 2.4 2.7 3.0 3.3 3.6 3.9 f cp = 20 mhz f cp = 16 mhz f cp = 12.5 mhz f cp = 10 mhz f cp = 4 mhz f cp = 2 mhz f cp = 1 mhz t a = + 25 c i cc (ma) v cc (v) 2.4 2.7 3.0 3.3 3.6 3.9 t a = + 25 c i ccs (ma) v cc (v) f cp = 20 mhz f cp = 16 mhz f cp = 12.5 mhz f cp = 10 mhz f cp = 4 mhz f cp = 2 mhz f cp = 1 mhz 35 30 25 20 15 10 5 0 i cc - v cc i ccs - v cc 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 i cch ( m a) v cc (v) t a = + 25 c 40 35 30 25 20 15 10 5 0 2.4 2.7 3.0 3.3 3.6 3.9 i ccl ( m a) v cc (v) t a = + 25 c i cch - v cc i ccl - v cc 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3.0 3.3 3.6 3.9 i cct ( m a) v cc (v) t a = + 25 c i cct - v cc
mb90470 series 113 ? flash versions (continued) 70 60 50 40 30 20 10 0 2.4 2.7 3.0 3.3 3.6 3.9 t a = + 25 c i cc (ma) v cc (v) f cp = 20 mhz f cp = 16 mhz f cp = 10 mhz f cp = 4 mhz f cp = 2 mhz 25 20 15 10 5 0 2.4 2.7 3.0 3.3 3.6 3.9 t a = + 25 c i ccs (ma) v cc (v) f cp = 20 mhz f cp = 16 mhz f cp = 10 mhz f cp = 4 mhz f cp = 2 mhz i cc - v cc i ccs - v cc 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.4 2.7 3.0 3.3 3.6 3.9 i cch ( m a) v cc (v) t a = + 25 c 30 25 20 15 10 5 0 2.4 2.7 3.0 3.3 3.6 3.9 i cchl ( m a) v cc (v) t a = + 25 c i cch - v cc i ccl - v cc 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3.0 3.3 3.6 3.9 i cct ( m a) v cc (v) t a = + 25 c i cct - v cc
mb90470 series 114 (continued) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.4 2.7 3.0 3.3 3.6 3.9 i a (ma) av cc (v) t a = + 25 c 100 90 80 70 60 50 40 30 20 10 0 2.4 2.7 3.0 3.3 3.6 3.9 i r (ma) av cc (v) t a = + 25 c i a - av cc i r - av cc r (k w ) 2.4 2.7 3.0 3.3 3.6 3.9 v cc (v) 1000 100 10 t a = + 25 c r - v cc
mb90470 series 115 n ordering information part number package remarks mb90473pf mb90474pf mb90477pf mb90478pf mb90f474lpf mb90f474hpf 100-pin plastic qfp (fpt-100p-m06) mb90473pfv mb90474pfv mb90477pfv mb90478pfv mb90f474lpfv MB90F474HPFV 100-pin plastic lqfp (fpt-100p-m05)
mb90470 series n package dimensions (continued) 100-pin plastic qfp (fpt-100p-m06) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2002 fujitsu limited f100008s-c-5-5 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) 14.000.20 (.551.008) 17.900.40 (.705.016) index 0.65(.026) 0.320.05 (.013.002) m 0.13(.005) "a" 0.170.06 (.007.002) 0.10(.004) details of "a" part (.035.006) 0.880.15 (.031.008) 0.800.20 0.25(.010) 3.00 +0.35 C0.20 +.014 C.008 .118 (mounting height) 0.250.20 (.010.008) (stand off) 0~8 ? * *
mb90470 series 117 (continued) 100-pin plastic lqfp (fpt-100p-m05) note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited f100007s-c-4-6 14.000.10(.551.004)sq 16.000.20(.630.008)sq 125 26 51 76 50 75 100 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.0057.0022) 0.08(.003) "a" index .059 C.004 +.008 C0.10 +0.20 1.50 (mounting height) 0 ? ~8 ? 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 0.100.10 (.004.004) details of "a" part (stand off) *
mb90470 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu or any third party or does fujitsu warrant non-infringement of any third-partys intellectual property right or other right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f030 3 ? fujitsu limited printed in japan

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